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參數(shù)資料
| 型號： | W78CE354 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | MONITOR MICROCONTROLLER |
| 中文描述： | 顯示器單片機 |
| 文件頁數(shù)： | 31/44頁 |
| 文件大小： | 426K |
| 代理商： | W78CE354 |
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W78C354
Publication Release Date: October 1996
- 31 -
Revision A1
H/V
Frequency
Counter
AD[7:0]
1
0
0
0
0
0
1
1
1
1
VSPS
HSPS
DUMMYEN
ENVS
VIN
HIN
VDISHC
Polarity
Detect &
Restoration
VREST
HREST
Sync
Separator
VSEP
VDUMMY
HDUMMY
H/V Dummy
Sync
Generator
VOUT
HOUT
H - Clamp
SOA
H-Clamp
Generator
SOA
Generator
Figure 11. Sync processor
M-1. Polarity Detector
The H/V polarity is detected automatically and can be read from SFR STATUS. The polarity of the
H/V input signals is then restored (they signals become HREST/VREST) for internal processing and
output to HOUT/VOUT to drive the deflection circuit.
Maximum sync width to HIN pin: (1/F
CLOCK
)
×
2
14
Maximum sync width to VIN pin: (1/F
CLOCK
)
×
2
14
FCLOCK
16 MHz
18.432 MHz
20 MHz
Max. sync width for HIN
1024
μ
S
1024
μ
S
888
μ
S
888
μ
S
819
μ
S
819
μ
S
Max. sync width for V
IN
M-2. Sync Separator
Vsync is separated from the composite sync automatically, without any additional software
programming. Figure 12 shows the waveforms of V
OUT
that result from a composite or non-composite
Hsync input.
If ENVS = 1, the limitations on the Vsync signal are:
V
IN
pulse width must be larger than Wvmin = [(1/F
CLOCK
)
128.5]
±
1/(2
×
F
CLOCK
)
V
OUT
is delayed from V
IN
signal by Tdelay = [(1/F
CLOCK
)
128.5]
±
1/(2
×
F
CLOCK
)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W78CE354E | 制造商:WINBOND 制造商全稱:Winbond 功能描述:MONITOR MICROCONTROLLER |
| W78CE354P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:MONITOR MICROCONTROLLER |
| W78CSX2 | 制造商:Magnecraft 功能描述:3-5 Days |
| W78CSX-2 | 制造商:Magnecraft 功能描述:Relay Electromechanical 4PDT 12 VDC Plug In |
| W78CSX-3 | 制造商:MAGNECRAFT 功能描述: |
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