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參數(shù)資料
| 型號： | W77LE58P-25 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 49/81頁 |
| 文件大小： | 657K |
| 代理商： | W77LE58P-25 |
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Preliminary W77LE58
Publication Release Date: August 1999
- 49 - Revision A1
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the
overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the
hardware when the timer interrupt is serviced. The Timer 2 interrupt is generated by a logical OR of
the TF2 and the EXF2 flags. These flags are set by overflow or capture/reload events in the timer 2
operation. The hardware does not clear these flags when a timer 2 interrupt is executed. Software has
to resolve the cause of the interrupt between TF2 and EXF2 and clear the appropriate flag.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the
time-out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the interrupt
is enabled by the enable bit EIE.4, then an interrupt will occur.
The Serial block can generate interrupts on reception or transmission. There are two interrupt sources
from the Serial block, which are obtained by the RI and TI bits in the SCON SFR and RI_1 and TI_1
in the SCON1 SFR. These bits are not automatically cleared by the hardware, and the user will have
to clear these bits using software.
All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to
disable all the interrupts, except PFI, at once.
Priority Level Structure
There are three priority levels for the interrupts, highest, high and low. The interrupt sources can be
individually set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted
by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the interrupts
themselves. This hierarchy comes into play when the interrupt controller has to resolve simultaneous
requests having the same priority level. This hierarchy is defined as shown below; the interrupts are
numbered starting from the highest priority to the lowest.
Table 7. Priority structure of interrupts
Source
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
Timer 2 Overflow
Serial Port 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog Timer
Flag
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
RI_1 + TI_1
IE2
IE3
IE4
IE5
WDIF
Priority level
1(highest)
2
3
4
5
6
7
8
9
10
11
12 (lowest)
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| W78L51 | 8-BIT MICROCONTROLLER |
| W78L51-24 | 8-BIT MICROCONTROLLER |
| W78L51P-24 | 8-BIT MICROCONTROLLER |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W77M032A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-BIT MICROCONTROLLER |
| W77M032A25DL | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-BIT MICROCONTROLLER |
| W77M032A25FL | 功能描述:IC MCU 8-BIT 1K SRAM 44-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:W77 標準包裝:60 系列:PSOC® 3 CY8C38xx 核心處理器:8051 芯體尺寸:8-位 速度:67MHz 連通性:EBI/EMI，I²C，LIN，SPI，UART/USART 外圍設備:電容感應，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):25 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:2K x 8 RAM 容量:8K x 8 電壓 - 電源 (Vcc/Vdd):1.71 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 2x20b，D/A 4x8b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFQFN 裸露焊盤 包裝:托盤 |
| W77M032A25PL | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-BIT MICROCONTROLLER |
| W780 | 制造商:LUMINIS 制造商全稱:LUMINIS 功能描述:Ceiling mount |
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