參數(shù)資料
型號(hào)： W77LE58F-25
廠商： WINBOND ELECTRONICS CORP
元件分類： 微控制器/微處理器
英文描述： 8 BIT MICROCONTROLLER
中文描述： 8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁(yè)數(shù)： 13/81頁(yè)
文件大?。?/td> 657K
代理商： W77LE58F-25
Preliminary W77LE58
Publication Release Date: August 1999
- 13 - Revision A1
Power Control
Bit:
7
6
5
4
3
2
1
0
SM0D
SMOD0
-
-
GF1
GF0
PD
IDL
Mnemonic: PCON
Address: 87h
SMOD : This bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1.
SMOD0: Framing Error Detection Enable: When SMOD0 is set to 1, then SCON.7(SCON1.7)
indicates a Frame Error and acts as the FE(FE_1) flag. When SMOD0 is 0, then
SCON.7(SCON1.7) acts as per the standard 8052 function.
GF1-0: These two bits are general purpose user flags.
PD:
Setting this bit causes the W77LE58 to go into the POWER DOWN mode. In this mode all
the clocks are stopped and program execution is frozen.
IDL:
Setting this bit causes the W77LE58 to go into the IDLE mode. In this mode the clocks to the
CPU are stopped, so program execution is frozen. But the clock to the serial, timer and
interrupt blocks is not stopped, and these blocks continue operating.
Timer Condtrol
Bit:
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Mnemonic: TCON
Address: 88h
TF1:
Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when
the program does a timer 1 interrupt service routine. Software can also set or clear this bit.
Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.
Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when
the program does a timer 0 interrupt service routine. Software can also set or clear this bit.
Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off.
TR1:
TF0:
TR0:
IE1:
Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1. This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
IT1:
IE0:
Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0 . This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
IT0:
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