
Preliminary W77IE58
- 70 -
The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a
best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By
using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise
rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then
this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks for
a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also detected
and shifted into the SBUF.
After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and
RI is set. However certain conditions must be met before the loading and setting of RI can be done.
1. RI must be 0 and
2. Either SM2 = 0, or the received stop bit = 1.
If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.
Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to
looking for a 1-to-0 transition on the RxD pin.
SBUF
RB8
Transmit Shift Register
Receive Shift
Register
TX SHIFT
PAROUT
D8
Internal
Data Bus
Internal
Data
Bus
TXD
RXD
Serial Port
Interrupt
SMOD=
(SMOD_1)
TCLK
RCLK
SAMPLE
Write to
SBUF
TX START
SOUT
0
1
0
1
TI
1
0
PARIN
STOP
START
LOAD
CLOCK
Read
SBUF
Timer 2 Overflow
(for Serial Port 0 only)
Timer 1
Overflow
TX CLOCK
RI
SERIAL
CONTROLLER
RX CLOCK
LOAD
SBUF
RX
START
RX SHIFT
2
16
1-TO-0
DETECTOR
BIT
DETECTOR
16
CLOCK
SIN
Figure 21. Serial Port Mode 1