- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363895 > W77IE58 (WINBOND ELECTRONICS CORP) 8-BIT MICROCONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | W77IE58 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 25 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 55/90頁 |
| 文件大?。?/td> | 409K |
| 代理商： | W77IE58 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當(dāng)前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁
Preliminary W77IE58
Publication Release Date: July 2000
- 55 -
Revision A1
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the overflow
in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware when the
timer interrupt is serviced. The Timer 2 interrupt is generated by a logical OR of the TF2 and the EXF2
flags. These flags are set by overflow or capture/reload events in the timer 2 operation. The hardware
does not clear these flags when a timer 2 interrupt is executed. Software has to resolve the cause of the
interrupt between TF2 and EXF2 and clear the appropriate flag.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the time-
out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the interrupt is
enabled by the enable bit EIE.4, then an interrupt will occur.
The Serial block can generate interrupts on reception or transmission. There are two interrupt sources
from the Serial block, which are obtained by the RI and TI bits in the SCON SFR and RI_1 and TI_1 in
the SCON1 SFR. These bits are not automatically cleared by the hardware, and the user will have to
clear these bits using software.
All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to disable
all the interrupts, except PFI, at once.
Priority Level Structure
There are three priority levels for the interrupts, highest, high and low. The interrupt sources can be
individually set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted by a
lower priority interrupt. However there exists a pre-defined hierarchy amongst the interrupts themselves.
This hierarchy comes into play when the interrupt controller has to resolve simultaneous requests having
the same priority level. This hierarchy is defined as shown below; the interrupts are numbered starting
from the highest priority to the lowest.
Table 7. Priority structure of interrupts
Source
Flag
Priority level
External Interrupt 0
IE0
1(highest)
Timer 0 Overflow
TF0
2
External Interrupt 1
IE1
3
Timer 1 Overflow
TF1
4
Serial Port
RI + TI
5
Timer 2 Overflow
TF2 + EXF2
6
Serial Port 1
RI_1 + TI_1
7
External Interrupt 2
IE2
8
External Interrupt 3
IE3
9
External Interrupt 4
IE4
10
External Interrupt 5
IE5
11
Watchdog Timer
WDIF
12 (lowest)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W77L32 | 8-BIT MICROCONTROLLER |
| W77LE532 | 8 BIT MICROCONTROLLER |
| W77LE58 | 8 BIT MICROCONTROLLER |
| W77LE58-25 | 8 BIT MICROCONTROLLER |
| W77LE58F-25 | 8 BIT MICROCONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W77IE58_06 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-BIT MICROCONTROLLER |
| W77J_1G WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| W77J_2GST WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| W77J_3G WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| W77L032A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-BIT MICROCONTROLLER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。