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參數(shù)資料
| 型號： | W49L102Q-12 |
| 英文描述： | EEPROM|FLASH|64KX16|CMOS|TSSOP|40PIN|PLASTIC |
| 中文描述： | 的EEPROM | FLASH動畫| 64KX16 |的CMOS | TSSOP封裝| 40PIN |塑料 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 275K |
| 代理商： | W49L102Q-12 |
W49L102
- 4 -
Program Operation
The W49L102 is programmed on a word-by-word basis. Program operation can only change logical
data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot block
from "0" to "1" is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will internally enter the program operation immediately after the word-
program command is entered. The internal program timer will automatically time-out (60
μ
S max. -
T
BP
) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to
detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49L102 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The programming and read operation are inhibited when V
DD
is
less than 1.8V typical.
(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) V
DD
power-on delay: When V
DD
has reached its sense level, the device will automatically time-out
10 mS before any write (erase/program) operation.
Data Polling (DQ
7 &
DQ
15
)- Write Status Detection
The W49L102 includes a data polling feature to indicate the end of a program or erase cycle.
When the W49L102 is in the internal program or erase cycle, any attempt to read DQ
7
or DQ
15
of the
last word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ
7
or DQ
15
will show the true data. Note that DQ
7
or DQ
15
will show logical "0" during the
erase cycle, and become logical "1" or true data when the erase cycle has completed.
Toggle Bit (DQ
6
& DQ
14
)- Write Status Detection
In addition to data polling, the W49L102 provides another method for determining the end of a program
cycle. During the internal program or erase cycle, any consecutive attempts to read DQ
6
or DQ
14
will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the
product ID. A read from address 0000H outputs the manufacturer code (00DAh). A read from address
0001H outputs the device code (002Fh). The product ID operation can be terminated by a three-word
command sequence or an alternate one-word command sequence (see Command Definition table).
In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE
high, and raising A9 to 12 volts.
Note: The hardware SID read function is not included in all parts; please refer to Ordering Information for details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W49L102Q-12B | x16 Flash EEPROM |
| W49L401 | FLASH |
| W49L401S-70B | EEPROM |
| W49L401T-70B | EEPROM |
| W49L401TS70B | EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W49L102Q-12B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM |
| W49L102Q-55 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 16 CMOS 3.3V FLASH MEMORY |
| W49L102Q-55B | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 16 CMOS 3.3V FLASH MEMORY |
| W49L102Q-70 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 16 CMOS 3.3V FLASH MEMORY |
| W49L102Q-70B | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 16 CMOS 3.3V FLASH MEMORY |
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