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參數(shù)資料
| 型號(hào)： | W48C101 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Spread Spectrum BX System Frequency Generator |
| 中文描述： | 擴(kuò)頻顏Bx系統(tǒng)頻率發(fā)生器 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 112K |
| 代理商： | W48C101 |
PRELIMINARY
Spread Spectrum BX System Frequency Generator
W48C101-01
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 7, 1999, rev. **
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Four copies of CPU output
Eight copies of PCI output (Synchronous w/CPU
output)
Two copies of 14.318-MHz IOAPIC output
Two copies of 48-MHz USB output
Three buffered copies of 14.318-MHz reference input
Input is a 14.318-MHz XTAL or reference signal
Selectable 100-MHz or 66-MHz CPU outputs
Power management control input pins
Test mode and output three-state capability
Key Specifications
Supply Voltages: .......................................V
DDQ3
= 3.3V±5%
V
DDQ2
= 2.5V±5%
CPU0:3 Jitter (Cycle to Cycle):................................... 200 ps
CPU0:3 Clock Skew: ...................................................175 ps
PCI_F, PCI1:7 Clock Skew: .........................................500 ps
CPU to PCI Clock Skew: ..............1.5 to 4.0 ns (CPU Leads)
Logic inputs have 250-k
pull-up resistors except SEL100/66#.
Table 1. Pin Selectable Frequency
SEL
100/66#
SEL1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
SEL0
0
1
0
1
0
1
0
1
CPU
(MHz)
HI-Z
66.6
66.6
66.6
X1/2
100
100
100
PCI
(MHz)
HI-Z
33.3
33.3
33.3
X1/6
33.3
33.3
33.3
SPREAD#=0
Don’t Care
±0.9% Center
–1% Down
–0.5% Down
Don’t Care
±0.9% Center
–1% Down
–0.5% Down
Pin Configuration
Block Diagram
REF0
REF1
GND
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
VDDQ3
GND
VDDQ3
48MHz
48MHz
GND
VDDQ3
REF2
VDDQ2
APIC0
APIC1
GND
NC
VDDQ2
CPU0
CPU1
GND
VDDQ2
CPU2
CPU3
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWR_DWN#
SPREAD#
SEL0
SEL1
SEL100/66#
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDQ3
REF0
VDDQ2
APIC0
CPU0
CPU1
CPU2
CPU3
PCI_F
XTAL
OSC
PLL Ref Freq
PLL 1
SEL100/66#
X2
X1
REF1
VDDQ3
Stop
Clock
Control
Stop
Clock
Control
PCI1
PWR_DWN#
Power
Down
Control
PCI2
PCI3
PCI4
PCI5
48MHz
48MHz
PLL2
÷2/÷3
REF2
VDDQ2
PCI_STOP#
CPU_STOP#
PCI6
PCI7
VDDQ3
APIC1
SEL0
SEL1
SPREAD#
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