參數(shù)資料
型號(hào)： W25Q64CVZPAP
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 64M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝： 6 X 5 MM, GREEN, WSON-8
文件頁(yè)數(shù)： 50/79頁(yè)
文件大?。?/td> 1086K
代理商： W25Q64CVZPAP
W25Q64CV
- 54 -
7.2.33 Read Manufacturer / Device ID Quad I/O (94h)
The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID
at 4x speed.
The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h” followed by a
24-bit address (A23-A0) of 000000h, 8-bit Continuous Read Mode Bits and then four clock dummy cycles,
with the capability to input the Address bits four bits per clock. After which, the Manufacturer ID for
Winbond (EFh) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most
significant bit (MSB) first as shown in Figure 31. The Device ID values for the W25Q64CV is listed in
Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID
will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving /CS high.
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (94h)
High Impedance
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
5
1
4
0
23
Mode 0
Mode 3
IOs switch from
Input to Output
High Impedance
7
3
6
2
/CS
CLK
IO
0
IO
1
IO
2
IO
3
High Impedance
A23-16
A15-8
A7-0
(00h)
M7-0
MFR ID
Device ID
Dummy
/CS
CLK
IO
0
IO
1
IO
2
IO
3
23
0
1
2
3
5
1
4
0
7
3
6
2
5
1
4
0
7
3
6
2
5
1
4
0
7
3
6
2
5
1
4
0
7
3
6
2
5
1
4
0
7
3
6
2
5
1
4
0
7
3
6
2
5
1
4
0
7
3
6
2
5
1
4
0
7
3
6
2
5
1
4
0
7
3
6
2
24
25
26
27
28
29
30
MFR ID
Device ID
(repeat)
MFR ID
Device ID
(repeat)
Figure 31. Read Manufacturer / Device ID Quad I/O Diagram
Note:
The “Continuous Read Mode” bits M7-0 must be set to Fxh to be compatible with Fast Read Quad I/O instruction.
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參數(shù)描述
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