- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68427 > W25Q16CVSSIG (WINBOND ELECTRONICS CORP) 16M X 1 SPI BUS SERIAL EEPROM, PDSO8 PDF資料下載
參數(shù)資料
| 型號(hào)： | W25Q16CVSSIG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 16M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.208 INCH, GREEN, SOIC-8 |
| 文件頁數(shù)： | 31/79頁 |
| 文件大?。?/td> | 1131K |
| 代理商： | W25Q16CVSSIG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁
W25Q16CV
Publication Release Date: April 01, 2011
- 37 -
Revision C
7.2.17 Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are
not required, which further reduces the instruction overhead allowing even faster random access for code
execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word
Read Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 16a. The
upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through
the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the E3h instruction code, as shown in Figure 16b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before
issuing normal instructions (See 7.2.20 for detail descriptions).
M7-0
/CS
CLK
Mode 0
Mode 3
0
1
IO
0
IO
1
IO
2
IO
2
3
4
5
20
16
12
8
21
17
22
18
23
19
13
9
14
10
15
11
A23-16
6
7
8
9
4
0
5
1
6
2
7
3
A15-8
A7-0
4
Byte 1
Byte 2
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
10
11
12
13
14
4
5
6
7
IOs switch from
Input to Output
Byte 3
15
16
17
18
19
20
21
Instruction (E3h)
4
0
5
1
6
2
7
3
Byte 4
Figure 16a. Octal Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4
≠ 10)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W25Q16DWZPIP | 16M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| W25Q20BWUXIP | 2M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| W25Q32BVSSAG | 32M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| W25Q32BVSSAP | 32M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| W25Q32BWSNIP | 4M X 8 SPI BUS SERIAL EEPROM, DSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q16CVSSIG TR | 制造商:Winbond Electronics Corp 功能描述:SPIFLASH, 16M-BIT, 4KB UNIFORM |
| W25Q16CVSSIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q16CVTCAG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q16CVTCAP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q16CVTCIG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。