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參數(shù)資料
| 型號： | VV6300 |
| 英文描述： | Integrated CMOS Colour Image Sensor with on-chip ADC. |
| 中文描述： | 集成CMOS彩色圖像傳感器芯片的ADC。 |
| 文件頁數(shù)： | 12/50頁 |
| 文件大小： | 499K |
| 代理商： | VV6300 |
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VV5301 & VV6301
Auto Black Calibration
cd5301_6301f-3-0.fm
Commercial in confidence
12/50
4.
Black calibration is used to remove voltage offsets that cause shifts in the black level of the video signal. The VV5/6301 is
equipped with an automatic function that continually monitors the output black level and calibrates if it has moved out of range.
The signal is corrected using two “Black-Cal” DACs, B0 and B1, shown below
Auto Black Calibration
Figure 5 : Block Diagram of Black Calibration System
Black calibration can be split into two stages,
monitor
(1 cycle over 2 lines) and
update
(3 cycles, each cycle takes 2 lines).
During the monitor phase the current black level is compared against two threshold values. If the current value falls outside the
threshold window then an update cycle is triggered. The update cycle can also be triggered by a change in the gain applied to
sensor core or via the serial interface.
4.1
The decision on when to re-calibrate the black level is made during the first cycle through the black reference lines. The decision
area for the black monitor is by default the last 16 pixels of the middle 128 pixels of the second designated black line, line 2.
However if this set of pixels fail to give a “good” black level then it is possible to use the penultimate group of 16 pixels.
Monitor Procedure
The black reference pixels are summed, averaged and then compared with the monitor window. If the average falls outside the
window a flag is then set to force a re-calibration of the DAC values.
4.2
The black calibration update sequence requires three phases and is performed over the remaining black lines at the start of the
video field, lines 3 to 8. During the first phase initial B0 DAC calibration is performed. In the second, the B1 DAC is calibrated
within the limitation of its step size. In the final phase the black level is fine tuned by re-calibrating the BO DAC.This is due to the
B1 DAC having a relatively coarse step size when high gain is applied.
Update
The two calibration phases for the B0 DAC differ in that the first time it is calibrated it is working on common mode data. During
the final phase the B0 DAC is fine-tuned using black reference pixels.
G2:0]
DATA[7:0]
S/H
amp
ADCLK
Blk
Sig
8bit ADC
B1 DAC (8bit)
B0 DAC (8bit)
Vsig
Vref
From Sensor
Array
ADSAM
to digital logic
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