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參數(shù)資料
| 型號： | VSP2230Y |
| 英文描述： | CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS |
| 中文描述： | CCD信號處理器的數(shù)碼相機(jī) |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 225K |
| 代理商： | VSP2230Y |
VSP2230
SLAS319
–
MAY 2001
7
www.ti.com
optical black (OB) level clamp loop (continued)
The OB clamp level (the pedestal level) is programmable through the serial interface, refer to
serial interface
for details. Table 1 shows the relationship between the input code and the OB clamp level.
The active polarity of CLPOB (active high or active low) can be chosen through the serial interface, refer to
serial
interface
for details. The default value of CLPOB is active low.
However, right after power on, this value is unknown. For this reason, it must be set to the appropriate value
by using the serial interface, or reset to the default value by the RESET pin. The description and the timing
diagrams in this data sheet are all based on the polarity of active low (default value).
Table 1. Programmable OB Clamp Level
INPUT CODE
OB CLAMP LEVEL, LSBs of 10-Bits
0000
0 LSB
0001
4 LSB
0010
8 LSB
0011
12 LSB
0100
16 LSB
0101
20 LSB
0110
24 LSB
0111
28 LSB
1000 (Default)
32 LSB
1001
36 LSB
1010
40 LSB
1011
44 LSB
1100
48 LSB
1101
52 LSB
1110
56 LSB
1111
60 LSB
preblanking and data latency
Some CCDs have large transient output signals during blanking intervals. Such signals may exceed the
VSP2230
’
s 1-V
P
–
P
input signal range and would overdrive the VSP2230 into saturation. Recovery time from
the saturation could be substantial. To avoid this, the VSP2230 has an input blanking (or preblanking) function.
When PBLK goes to low, the CCDIN input is disconnected from the internal CDS stage and large transients are
prevented from passing through. The VSP2230
’
s digital outputs will go to all zeros at the 11th rising edge of
ADCCK from just after PBLK set to low to accommodate the clock latency of the VSP2230. In this mode, the
digital output data comes out at the rising edge of ADCCK with a delay of 11 clock cycles (data latency is 11).
In the normal operation mode, it is different from the preblanking mode. The digital output data comes out at
the rising edge of ADCCK with a delay of nine clock cycles (data latency is 9).
In order to keep stable and accurate OB clamp level, CLPOB should not be activated during PBLK active period.
Since CCDIN input is disconnected from the internal circuit, even if the autocalibration loop should be closed
while CLPOB is active. Then the OB clamp level is different from the actual OB level established by the CCD
imager output. The missed OB clamp level would affect the picture quality.
If the input voltage is higher than the supply rail by 0.3 V or lower than the ground rail by 0.3 V, the protection
diodes will be turned on to prevent the input voltage from going further. Such a high swing signal may cause
a device damage to the VSP2230 and should be avoided.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSP2230Y/2K | 功能描述:視頻 IC 10-Bit 36Msps Signal Processor RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2230Y/2KG4 | 功能描述:視頻 IC 10-Bit 36Msps Signal Processor RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2230YG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10-Bit 36Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP2232 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS |
| VSP2232Y | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 12-Bit 36Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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