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參數(shù)資料
| 型號： | VSP2230Y |
| 英文描述： | CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS |
| 中文描述： | CCD信號處理器的數(shù)碼相機(jī) |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 225K |
| 代理商： | VSP2230Y |
VSP2230
SLAS319
–
MAY 2001
4
www.ti.com
detailed description
introduction
The VSP2230 is a complete mixed-signal IC that contains all of the key features associated with the processing
of the CCD imager output signal in a video camera, a digital still camera, a security camera, or similar
applications. A simplified block diagram is shown on the front page of this data sheet. The VSP2230 includes
a correlated double sampler (CDS), a programmable gain amplifier (PGA), an analog-to-digital converter
(ADC), an input clamp, an optical black (OB) level clamp loop, a serial interface, a timing control, and a reference
voltage generator. We recommend an off-chip emitter follower buffer between the CCD output and the VSP2230
CCDIN input. The PGA gain control, the clock polarity setting, and the operation mode choosing can be made
through the serial interface. All parameters are reset to the default value when the RESET pin goes to low
asynchronously from the clocks.
correlated double sampler (CDS)
The output signal of a CCD imager is sampled twice during one pixel period, one at the reference interval and
the other at the data interval.
Subtracting these two samples, extracts the video information of the pixel as well as removes any noise that
is common
—
or correlated
—
to both the intervals.
Thus, a CDS is very important to reduce the reset noise and the low frequency noises that are present on the
CCD output signal. Figure 1 shows the simplified block diagram of the CDS and input clamp.
_
+
OPA
C(1) = 5 pF
C(2) = 5 pF
SHP
SHD
REFN (1.25 V)
VSP2230
CCDIN
CLPDM
SHP
CIN
CCD
Output
Figure 1. Simplified Block Diagram of the CDS and Input Clamp
The CDS is driven through an off-chip coupling capacitor (C
IN
). AC coupling is strongly recommended because
the DC level of the CCD output signal is usually too high (several volts) for the CDS to work properly. A 0.1-
μ
F
capacitor is recommended for C
IN
, however, it depends on the application environment.
Also, an off-chip emitter follower buffer is recommended that can drive more than 10 pF, because the 5 pF of
the sampling capacitor and a few pF of stray capacitance can be seen at the input pin. The analog input signal
range at the CCDIN pin is 1 V
P
–
P
, and the appropriate common mode voltage for the CDS is around 0.5 V to
1.5 V.
The reference level is sampled during SHP active period, and the voltage level is held on the sampling capacitor
C
(1)
at the trailing edge of SHP. The data level is sampled during SHD active period, and the voltage level is
held on the sampling capacitor C
(2)
at the trailing edge of SHD. Then, the switched-capacitor amplifier performs
the subtraction of these two levels.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSP2230Y/2K | 功能描述:視頻 IC 10-Bit 36Msps Signal Processor RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2230Y/2KG4 | 功能描述:視頻 IC 10-Bit 36Msps Signal Processor RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2230YG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10-Bit 36Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP2232 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS |
| VSP2232Y | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 12-Bit 36Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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