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參數(shù)資料
| 型號： | VSP2210Y |
| 英文描述： | CCD SIGNAL PROCESSOR For Digital Cameras |
| 中文描述： | CCD信號處理器的數(shù)碼相機(jī) |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 123K |
| 代理商： | VSP2210Y |
7
VSP2210
THEORY OF OPERATION
INTRODUCTION
The VSP2210 is a complete mixed-signal IC that contains
all of the key features associated with the processing of the
CCD imager output signal in a video camera, a digital still
camera, security camera, or similar applications. A simpli-
fied block diagram is shown in the front page of this data
sheet. The VSP2210 includes a correlated double sampler
(CDS), programmable gain amplifier (PGA), Analog-to-
Digital Converter (ADC), input clamp, optical black (OB)
level clamp loop, serial interface, timing control, reference
voltage generator, and general purpose 8-bit Digital-to-
Analog Converters (DAC). We recommend an off-chip
emitter follower buffer between the CCD output and the
VSP2210 CCDIN input. The PGA gain control, clock polar-
ity setting, and operation mode selection can be made
through the serial interface. All parameters are reset to the
default value when the RESET pin goes to LOW asynchro-
nously from the clocks.
CORRELATED DOUBLE SAMPLER (CDS)
The output signal of a CCD imager is sampled twice during
one pixel period: one at the reference interval and the other
at the data interval. Subtracting these two samples extracts
the video information of the pixel as well as removes any
noise that is common, or correlated, to both the intervals.
Therefore, the CDS is very important to reduce the reset
noise and the low-frequency noises that are present on the
CCD output signal. Figure 1 shows the simplified block
diagram of the CDS and input clamp.
A 0.1
μ
F capacitor is recommended for C
IN
, depending on
the application environment. Additionally, we recommend
an off-chip emitter follower buffer that can drive more than
10pF, because 10pF of the sampling capacitor and a few pF
of stray capacitance can be seen at the input pin. The analog
input signal range at the CCDIN pin is 1Vp-p, and the
appropriate common mode voltage for the CDS is around
0.5V to 1.5V.
The reference level is sampled during SHP active period,
and the voltage level is held on sampling capacitor C
1
at the
trailing edge of SHP. The data level is sampled during SHD
active period, and the voltage level is held on the sampling
capacitor C
2
at the trailing edge of SHD. The switched-
capacitor amplifier then performs the subtraction of these
two levels.
The active polarity of SHP/SHD (Active HIGH or Active
LOW) can be selected through the serial interface (refer to
“Serial Interface” section for more detail). The default value
of SHP/SHD is “Active LOW”. However, immediately after
power on, this value is “Unknown”. For this reason, the
appropriate value must be set by using the serial interface, or
reset to the default value by the RESET pin. The description
and the timing diagrams in this data sheet are all based on
the polarity of Active LOW (default value).
INPUT CLAMP OR DUMMY PIXEL CLAMP
The buffered CCD output is capacitively coupled to the
VSP2210. The purpose of the input clamp is to restore the
DC component of the input signal that was lost with the AC
coupling and establish the desired DC bias point for the
CDS. Figure 1 also shows a simplified block diagram of the
input clamp. The input level is clamped to internal reference
voltage CM (1.5V) during the dummy pixel interval. More
specifically, when both CLPDM and SHP are active, the
dummy clamp function becomes active. If the dummy pixels
and/or the CLPDM pulse is not available in your system, the
CLPOB pulse can be used in place of CLPDM, as long as the
clamping takes place during black pixels. In this case, both
the CPLDM pin (actives as same timing as CLPOB) and
SHP become active during the optical black pixel interval,
and then the dummy clamp function becomes active.
The active polarity of CLPDM and SHP (Active HIGH or
Active LOW) can be selected through the serial interface
(refer to the “Serial Interface” section for more detail).
The default value of CLPDM and SHP is “Active LOW”.
However, immediately after power on, this value is “Un-
known”. For this reason, the appropriate value must be set
by using the serial interface, or reset to the default value by
the RESET pin. The description and the timing diagrams in
this data sheet are all based on the polarity of Active LOW
(default value).
FIGURE 1. Simplified Block Diagram of CDS and Input
Clamp.
OPA
C
IN
C
10pF
C
10pF
CM (1.5V)
CCDIN
SHP
SHD
CCD
Output
SHP
CLPDM
VSP2210
The CDS is driven through an off-chip coupling capacitor
(C
IN
). AC coupling is strongly recommended because the
DC level of the CCD output signal is usually several volts
too high for the CDS to work properly.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSP2210Y/2K | 功能描述:視頻 IC 10-Bit 20 Msps Signal Processor RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2210Y/2KG4 | 功能描述:視頻 IC 10-Bit 20 Msps Signal Processor RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2210YG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10B 20Msps CCD Signal Proc RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP2212 | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2212Y | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 12-Bit 20 Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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