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參數(shù)資料
| 型號： | VSP2210Y |
| 英文描述： | CCD SIGNAL PROCESSOR For Digital Cameras |
| 中文描述： | CCD信號處理器的數(shù)碼相機 |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 123K |
| 代理商： | VSP2210Y |
11
VSP2210
TIMINGS
The CDS and the ADC are operated by SHP/SHD and their
derivative timing clocks generated by the on-chip timing
generator. The digital output data is synchronized with
ADCCK. The timing relationship among the CCD signal,
SHP/SHD, ADCCK and the output data is shown in the
VSP2210 “CDS Timing Specifications”. CLPOB is used to
activate the black level clamp loop during the OB pixel
interval, and CLPDM is used to activate the input clamping
during the dummy pixel interval. If the CLPDM pulse is not
available in your system, the CLPOB pulse can be used in
place of CLPDM as long as the clamping takes place during
black pixels (refer to the “Input Clamp and Dummy Pixel
Clamp” section for more detail). The clock polarities of
SHP/SHD, CLPOB and CLPDM can be independently set
through the serial interface (refer to the “Serial Interface”
section for more detail). The description and the timing
diagrams in this data sheet are all based on the polarity of
Active LOW (default value). In order to keep a stable and
accurate OB clamp level, we recommend CLPOB should
not be activated during PBLK active period. Refer to the
“Preblanking and Data Latency” section for more detail. In
Stand-By mode, all of ADCCK, SHP, SHD, CLPOB and
CLPDM are internally masked and pulled HIGH.
GENERAL-PURPOSE 8-BIT DIGITAL-TO-ANALOG
CONVERTER (DAC0,DAC1)
The VSP2210 incorporates two identical 8-bit Digital-to-
Analog converters (DACs). These DACs are for user-defin-
able options such as iris control and sub-bias voltage control
of the CCD imager. The input data for these DACs is set by
the written data through the serial interface (refer to the
“Serial Interface” section for more detail). DAC input data
that is all ZEROs corresponds to a minimum output voltage
of 0.1V. In a similar manner, all ONEs correspond to a
maximum output voltage of 2.9V. Figure 3 shows the
characteristics.
POWER SUPPLY, GROUNDING AND DEVICE
DECOUPLING RECOMMENDATIONS
The VSP2210 incorporates a very high-precision and high-
speed Analog-to-Digital converter and analog circuitry that
are vulnerable to any extraneous noise from the rails or
elsewhere. For this reason, it should be treated as an analog
component and all supply pins except for DRV
DD
should be
powered by the only analog supply of the system. This will
ensure the most consistent results, since digital power lines
often carry high level of wide band noise that would other-
wise be coupled into the device and degrade the achievable
performance. Proper grounding, short lead length and the
use of ground planes are also very important for high-
frequency designs. Multilayer PC boards are recommended
for the best performance, since they offer distinct advantages
like minimizing ground impedance, separation of signal
layers by ground layers, etc. It is highly recommended that
analog and digital ground pins of the VSP2210 be joined
together at the IC and be connected only to the analog
ground of the system. The driver stage of the digital outputs
(B[9:0]) is supplied through a dedicated supply pin (DRV
DD
)
and it should be separated from the other supply pins
completely, or at least with a ferrite bead. It is also recom-
mended to keep the capacitive loading on the output data
lines as low as possible (typically less than 15pF). Larger
capacitive loads demand higher charging current surges that
can feed back into the analog portion of the VSP2210 and
affect the performance. If possible, external buffers or latches
should be used, providing the added benefit of isolating the
VSP2210 from any digital noise activities on the data lines.
In addition, resistors in series with each data line may help
minimizing the surge current. Values in the range of 100
to 200
will limit the instantaneous current the output stage
has to provide for recharging the parasitic capacitances as
the output levels change from LOW to HIGH, or HIGH to
LOW. Due to high operation speed, the converter also
generates high-frequency current transients and noises that
are fed back into the supply and reference lines. This
requires the supply and reference pins be sufficiently by-
passed. In most cases, 0.1
μ
F ceramic chip capacitors are
adequate to decouple the reference pins. Supply pins should
be decoupled to the ground plane with a parallel combina-
tion of tantalum (1
μ
F to 22
μ
F) and ceramic (0.1
μ
F) capaci-
tors. The effectiveness of the decoupling largely depends on
the proximity to the individual pin. DRV
DD
should be
decoupled to the proximity of DRVGND. Special attention
must be paid to the bypassing of COB, BYPP2 and BYPM,
since these capacitor values determine important analog
performances of the device.
Input Control Code (0 to 255)
O
3.0
2.5
2.0
1.5
1.0
0.5
0
0
5
1
1
2
2
2
FIGURE 3. Characteristics for general-purpose 8-bit DAC
(DAC0, DAC1).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSP2210Y/2K | 功能描述:視頻 IC 10-Bit 20 Msps Signal Processor RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2210Y/2KG4 | 功能描述:視頻 IC 10-Bit 20 Msps Signal Processor RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2210YG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10B 20Msps CCD Signal Proc RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP2212 | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2212Y | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 12-Bit 20 Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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