參數(shù)資料
型號: VSP2210Y
英文描述: CCD SIGNAL PROCESSOR For Digital Cameras
中文描述: CCD信號處理器的數(shù)碼相機(jī)
文件頁數(shù): 4/11頁
文件大?。?/td> 123K
代理商: VSP2210Y
4
VSP2210
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
GNDA
GNDA
V
CC
V
CC
BYPM
BYP
CCDIN
BYPP2
COB
V
CC
GNDA
GNDA
S
S
S
R
D
D
G
G
V
C
R
R
C
D
D
D
G
A
G
V
C
P
C
S
S
C
V
C
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7
B8
B9 (MSB)
48
47
46
45
44
43
42
41
40
39
38
13
14
15
16
17
18
19
20
21
22
23
37
24
VSP2210
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
GNDA
GNDA
V
COB
BYPP2
CCDIN
BYP
BYPM
V
CC
V
CC
GNDA
GNDA
CM
REFP
REFN
V
CC
GNDA
GNDA
DACOUT0
P
P
P
Analog Ground
Analog Ground
Analog Power Supply
Optical Black Clamp Loop Reference (Bypass to Ground
(3)
)
Internal Reference P (Bypass to Ground
(4)
)
CCD Signal Input
Internal Reference C (Bypass to Ground
(5)
)
Internal Reference N (Bypass to Ground
(4)
)
Analog Power Supply
Analog Power Supply
Analog Ground
Analog Ground
A/D Converter Common-Mode Voltage (Bypass to Ground
(5)
)
A/D Converter Positive Reference (Bypass to Ground
(5)
)
A/D Converter Negative Reference (Bypass to Ground
(5)
)
Analog Power Supply
Analog Ground
Analog Ground
General-Purpose 8-Bit D/A Converter
(DAC0) Output Voltage
General-Purpose 8-Bit D/A Converter
(DAC1) Output Voltage
Asynchronous System Reset (Active LOW)
Serial Data Latch Signal (Triggered at the Rising Edge)
Serial Data Input
Clock for Serial Data Shift (Triggered at the Rising Edge)
AO
AO
AI
AO
AO
P
P
P
P
AO
AO
AO
P
P
P
AO
44
DACOUT1
AO
45
46
47
48
RESET
SLOAD
SDATA
SCLK
DI
DI
DI
DI
PIN
NAME
TYPE
(1)
DESCRIPTION
1
2
3
4
5
6
7
8
9
NC
NC
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
P
P
P
DI
P
P
DI
No Connection
No Connection
Bit 0, A/D Converter Output, Least Significant Bit
Bit 1, A/D Converter Output
Bit 2, A/D Converter Output
Bit 3, A/D Converter Output
Bit 4, A/D Converter Output
Bit 5, A/D Converter Output
Bit 6, A/D Converter Output
Bit 7, A/D Converter Output
Bit 8, A/D Converter Output
Bit 9, A/D Converter Output, Most Significant Bit
Power Supply, Exclusively for Digital Output
Digital Ground, Exclusively for Digital Output
Analog Ground
Clock for Digital Output Buffer
Analog Ground
Analog Power Supply
Preblanking:
HIGH = Normal Operation Mode
LOW = Preblanking Mode: Digital Output “All Zero”
Optical Black Clamp Pulse (Default = Active LOW
(2)
)
CDS Reference Level Sampling Pulse (Default = Active LOW
(2)
)
CDS Data Level Sampling Pulse (Default = Active LOW
(2)
)
Dummy Pixel Clamp Pulse (Default = Active LOW
(2)
)
Analog Power Supply
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7
B8
10
11
12 B9 (MSB)
13
DRV
14
DRVGND
15
GNDA
16
ADCCK
17
GNDA
18
19
PBLK
V
20
21
22
23
24
CLPOB
SHP
SHD
CLPDM
V
CC
DI
DI
DI
DI
P
PIN
NAME
TYPE
(1)
DESCRIPTION
PIN DESCRIPTIONS
NOTES: (1) Type designators: P = Power Supply and ground; DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output. (2) Refer to the “Serial
Interface” section for more detail. (3) Should be connected to ground with a bypass capacitor. We recommend the value of 0.1
μ
F to 0.22
μ
F, however, it depends
on the application environment. Refer to the “Optical Black Level Clamp Loop” section for more detail. (4) Should be connected to ground with a bypass capacitor.
We recommend the value of 1000pF, however, it depends on the application environment. Refer to the “Voltage Reference” section for more detail. (5) Should be
connected to ground with a bypass capacitor (0.1
μ
F). Refer to the “Voltage Reference” section for more detail.
Top View
LQFP
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