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參數(shù)資料
| 型號(hào)： | VSP2101 |
| 英文描述： | CCD SIGNAL PROCESSOR For Digital Cameras |
| 中文描述： | CCD信號(hào)處理器的數(shù)碼相機(jī) |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 184K |
| 代理商： | VSP2101 |
9
VSP2101
THEORY OF OPERATION
The VSP2101 is an integrated circuit that contains many of
the key features associated with the processing of analog
signals in a video camera or a digital-still camera. Figure 1
shows a simplified block diagram of the VSP2101.
The output from the CCD array is first sent to a Correlated
Double Sampler (CDS), then a voltage-controlled attenuator
with a logarithmic control characteristic, and an output
amplifier prior to being applied to the input of a 10-bit A/D
converter.
Two calibration cycles are employed to reduce the offset
variation of the VSP2101. During the dummy pixel time, an
input auto-zero circuit is activated that eliminates the offset
of the correlated double sampler. During the optical black
timing interval, another auto-zero circuit is employed to
eliminate the offset associated with the output amplifier and
the remaining offset from the CDS.
CORRELATED DOUBLE SAMPLER (CDS)
The CDS removes low frequency noise from the output of
the image sensor. Refer to Figure 2 which shows a block
diagram of the CDS. The output from the CCD array is
sampled during the reference interval as well as during the
data interval. Noise that is present at the input and is of a
period greater than the pixel interval will be eliminated by
subtraction.
The VSP2101 employs a three track/hold correlated double
sampler architecture. Track/Hold 2 is sampled during the
reference interval by the REFCK signal. Track/Hold 3 is
resampled at the same time that the data Track/Hold 1 is
sampled by the DATCK signal. This is done to remove large
transients from Track/Hold 2 that results from a portion of
the reset transient being present during the acquisition time
of this track and hold. The output of Track/Hold 2 is buffered
by a voltage follower.
FIGURE 2. Block Diagram of Correlated Double Sampler.
FIGURE 1. Simplified Block Diagram of VSP2101.
10-Bit
27MHz
A/D
VCA
CDS
Clamp
REFCK DATCK
Black Level
Auto-Zero
Loop
Dummy
Feedback
Loop
OB
Gain Control
DUMC
CCD Input
Output
Amplifier
Digital Output
ADCK
Data Sampling Channel
Reference Sampling
Channel
T/H1
T/H3
T/H2
1V
DUMC REFCK
CCD
Input
DATCK
To VCA
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| VSP2101Y | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10-Bit 27 Msps w/10-Bit On-Chip DAC RoHS:否 制造商:Texas Instruments 輸入信號(hào)類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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| VSP2101Y/2KG4 | 功能描述:視頻 IC 10-Bit 27 Msps w/10-Bit On-Chip DAC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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| VSP2210 | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL PROCESSOR For Digital Cameras |
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