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參數資料
| 型號： | VSP2101 |
| 英文描述： | CCD SIGNAL PROCESSOR For Digital Cameras |
| 中文描述： | CCD信號處理器的數碼相機 |
| 文件頁數： | 10/12頁 |
| 文件大?。?/td> | 184K |
| 代理商： | VSP2101 |
10
VSP2101
T =
C
(G
M
) (D)
FIGURE 4. Black Level Auto-Zero Loop.
DIFFERENCE AMPLIFIER
The correlated double sampler function is completed when
the output of the data and reference channel are sent to the
difference amplifier where the signals are subtracted. In
addition to providing the difference function, the difference
amplifier amplifies the signal by a factor of 2 which helps
to improve the overall signal-to-noise ratio. The difference
amplifier also generates a differential signal to drive the
voltage-controlled attenuator.
INPUT CLAMP
The output from the CCD array is capacitively coupled to the
VSP2101. To prevent shifts in the DC level from taking place
due to varying input duty cycles, the input capacitor is
clamped during the dummy pixel interval by the REFCK
signal and the DUMC signal. A P-channel transistor is used
for this input clamp switch to allow a 2V negative change at
the input that would bring the signal below ground by 1.
Under typical conditions, the bias at the input to the VSP2101
is at 1V.
DUMMY PIXEL AUTO-ZERO LOOP
The output from the data and reference channel is processed
by the previously mentioned difference amplifier. The dif-
ferential output from the difference amplifier is sent to both
the voltage-controlled logarithmic attenuator and to an error
amplifier. The error amplifier amplifies and feeds a signal to
the difference amplifier to drive the offset measured at the
output of the difference amplifier to zero. A block diagram
of this circuit is shown in Figure 3. This error amplifier
serves the purpose of reducing the offset of the CDS to avoid
a large offset from being amplified by the output amplifier.
The effective time constant of this loop is given by:
where R is 10k
, C is an external capacitor connected to pin
27 (CCD R), A is the gain of the error amplifier with a value
of 50, and D is the duty cycle of the time that the dummy
pixel auto-zero loop is in operation. The duty cycle (D) must
be considered as the loop operates in a sampled mode.
Operation of the dummy auto-zero loop is activated by the
DUMC signal that happens once during each horizontal line
interval.
TIMING
The REFCK and DATCK signals are used to operate the
CDS as previously explained. These same two signals are
also used by internal timing circuitry to create the necessary
timing signals for the A/D. The output from the A/D is read
out to external circuitry by the ADCK signal. DUMC is used
to activate the dummy pixel auto-zero loop and OB is used
to activate the black level auto-zero loop. The input digital
timing signals REFCK, DATCK, DUMC and OB are ca-
pable of being driven from either 3V or 5V logic levels.
VOLTAGE-CONTROLLED ATTENUATOR
To maximize the dynamic range of the VSP2101, a voltage-
controlled attenuator is included with a control range from
0dB to –34dB. The gain control has a logarithmic relation-
ship between the control voltage and the attenuation. The
attenuator processes a differential signal from the difference
amplifier to improve linearity and to reject both power supply
and common-mode noise. The output from the attenuator is
amplified by 28dB prior to being applied to the A/D. A
typical gain control characteristic of the VSP2101 is shown
in the typical performance curve, “VCA Characteristics”.
BLACK LEVEL AUTO-ZERO LOOP
The black level auto-zero loop amplifies the difference
between the output of the output amplifier and a reference
signal during the optical black timing interval. This differ-
ence signal is amplified and fed back into the output ampli-
fier to correct the offset. In doing so, the output level of the
entire CCD channel can be controlled to be approximately –
FS + 32LSBs under zero input signal conditions. The black
level auto-zero loop is activated by the OB timing signal.
Figure 4 shows a block diagram of the black level auto-zero
loop. The loop time constant is given by:
FIGURE 3. Block Diagram of Dummy Pixel Loop.
RC
AD
T =
OB
To ADS
32LSB
Error
Amplifier
Output Amplifier
G
M
From
VCA
C
C
DUMCK
To VCA
CDS
Error
Amplifier
A
CCD
IN
CCD R
C
R
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