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參數(shù)資料
| 型號： | VSP2101 |
| 英文描述： | CCD SIGNAL PROCESSOR For Digital Cameras |
| 中文描述： | CCD信號處理器的數(shù)碼相機 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 184K |
| 代理商： | VSP2101 |
11
VSP2101
where C is the external filter capacitance applied to pin 24
(C), G
M
is .001
and D is the duty cycle of the time that the
black level auto-zero loop is in operation. The duty cycle (D)
must be considered as the loop operates in a sampled mode.
Operation of the black level auto-zero loop is activated by
the OB signal that happens once during each horizontal line
interval.
A/D CONVERTER
The A/D converter utilizes a pipline architecture. The fully
differential topology and digital error correction guarantee
10-bit resolution. The A/D converter circuitry includes a
reference circuit that provides bias voltages for the entire
system.
SERIAL INTERFACE AND DACs
The VSP2101 incorporates two identical 10-bit DACs (DAC0
and DAC1). DAC0 is for controlling the amount of attenu-
ation of the log Voltage Controlled Attenuator (VCA) and
DAC1 is for user-defineable options such as iris control.
The input data for these DACs are set by the written data
through the serial interface. The serial port has an 12-bit
register which is controlled by four signals (SD, SCLK,
WRT, RESET). SD is the serial data input, SCLK is the
clock for the serial data, WRT pulse takes the serial register
data into another internal parallel register at the rising edge,
RESET resets all the registers’ data to zeros asynchronously
when RESET = LOW. The serial register uses master-slave
dual flip-flops and the master flip-flop receives the input
data at the rising edge of SCLK and transmits this data into
the slave at the falling edge of SCLK. Therefore, the clock
SCLK must be normally LOW.
When the DAC input data is all zeros, this corresponds to a
maximum output voltage of 2.4V. In a similar manner, all
ones correspond to a DAC output voltage of 0.3V. The VCA
attenuation is at a minimum—which is the same as the
channel gain being a maximum—when the DAC voltage is
at 2.4V.
The serial data format and the related signal timing are
shown page 5. When the input serial data is longer than 12
bits, the last 12 bits become effective and the former bits are
erased.
When the registers are reset, the user should be careful that
the channel gain setting becomes maximum and DAC1
output voltage goes to maximum.
DECOUPLING AND GROUNDING
CONSIDERATIONS
The VSP2101 has several supply pins, one of which is
dedicated to supply only the digital output driver (pin 12,
DRV
DD
). The remaining supply pins are not, as is often the
case, divided into analog and digital supply pins since they
are internally connected on the chip. For this reason, it is
recommended that the VSP2101 be treated as an analog
component and be powered from the analog supply only.
Digital supply lines often carry high levels of wide band
noise which can couple back into the VSP2101 and limit
performance.
Figure 5 shows the recommended decoupling scheme for the
VSP2101. In most cases, 0.1
μ
F ceramic chip capacitors are
adequate to keep the impedance low over a wide frequency
range. Their effectiveness largely depends on the proximity
to the individual pin. Therefore, they should be located as
close as possible to the pins. In addition, one larger capacitor
(1
μ
F to 22
μ
F) should be placed on the PC board in proxim-
ity of the VSP2101.
OTHER RECOMMENDATIONS
DRV
DD
is a power supply used exclusively for the digital
output driver and should not be connected to AV
DD
and
DV
DD
, even if the power supply voltage is the same. The
voltage level difference between DRV
DD
, AV
DD
, and DV
DD
should be kept less than 0.3V.
If your PC board has analog and digital ground, AV
SS
, DV
SS
,
and DRV
SS
should be connected to analog ground.
DEMONSTRATION BOARD
A demonstration board, DEM-VSP2101, is available to
assist in the inital evaluation of the circuit performance
using the VSP2101. The schematic of the DEM-VSP2101 is
shown in Figure 5.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSP2101Y | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10-Bit 27 Msps w/10-Bit On-Chip DAC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP2101Y/2K | 功能描述:視頻 IC 10-Bit 27 Msps w/10-Bit On-Chip DAC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2101Y/2KG4 | 功能描述:視頻 IC 10-Bit 27 Msps w/10-Bit On-Chip DAC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2101YG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10-Bit 27 Msps w/10-Bit On-Chip DAC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP2210 | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL PROCESSOR For Digital Cameras |
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