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參數(shù)資料
| 型號(hào)： | VSLI2002_1MB_MRAM |
| 英文描述： | A low power 1Mbit MRAM based on 1T1MTJ bit cell integration with copper interconnects |
| 中文描述： | 甲低功耗1Mbit的基礎(chǔ)上1T1MTJ的MRAM位單元集成銅互連 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大小： | 246K |
| 代理商： | VSLI2002_1MB_MRAM |
To be published at VLSI Symposium 2002
power-up sequence is required to put the chip into active
mode.
The 1Mb MRAM circuit is arranged in two 524kb
banks (see Fig. 9). Each bank contains sixteen 32Kb
blocks, with each block containing a mid-point reference
generator column (see Fig. 7). Within each block the mid-
point generator services sixteen bits to the left and sixteen
bits to the right of its column. The mid-point reference
generators are set to their operational states during the
initial power up sequence. The information in a target bit
is read by comparing the target bit resistance with the
associated mid-point reference generator. The read
operation is as follows: a memory cell is selected by
driving a wordline/digitline to vdd, selecting a column, and
turning on all ground switches. A current conveyor is
shared by every 32 bitlines and every reference bitline has
its own current conveyor. Once the current conveyors are
turned on, they clamp the target bitlines and reference
bitlines to their respective voltages, take the resulting target
and reference bitline currents and convert them to a voltage
signal with substantial boost. The target and reference
current conveyors form a differential pair and their outputs
are fed into a two stage differential comparator followed by
a regenerator, which again boosts the signal. The read
circuitry has been optimized to achieve high bandwidth,
maintain offset insensitivity, and consume minimal silicon
area. Read access times of 50ns have been measured at 3V
operation.
Fig. 8. Microphotograph showing Motorola’s 1Mb
MRAM circuit integrated with copper interconnects.
Columns
Columns
Select
DL
0
1024
0
1024
Column Select
Current/Source or Sink
Read Circuit
16
16
dq0
dq15
Column Select
Current/Source or Sink
Read Circuit
16
16
dq0
dq15
Decode
Source A
Current Switch
Current/Source or Sink
16
BL 511-0
Current Switch
Current/Source or Sink
16
BL 511-0
GL 0
GL 512
GL 0
GL 512
MRAM Array
512 columns
1024 Rows
16 Ref.
MRAM Array
512 columns
1024 Rows
16 Ref.
DL
Row
Row
Current
C
G
C
G
Fig. 9. Block diagram of 1Mb MRAM.
Summary
0.6
μ
m CMOS technology. This 1Mbit demonstration is
the largest MRAM circuit to date and the first using copper
interconnects and flux concentrating layers for a low power
operation. This demonstration was done on 200mm
substrates. A new reference cell for MRAM has been
demonstrated with excellent results.
References
[1] M. Durlam, P. Naji, M. DeHerrera, S. Tehrani, G.
Kerszykowski, and K. Kyler, “Nonvolatile RAM based on Magnetic
Tunnel Junction Elements”, ISSCC Digest of Technical Papers, PP.
130-131, Feb. 2000.
[2] P. Naji, M. Durlam, S. Tehrani, J. Calder, M. DeHerrera, “A
256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”, ISSCC
Digest of Technical Papers, PP. 122-123, Feb. 2001.
[3] R. Scheuerlein, W. Gallagher, S. Parkin, A. Lee, S. Ray, R.
Robertazzi, and W. Reohr, “A 10ns Read and Write Non-Volatile
Memory Array Using a Magnetic Tunnel Junction and FET Switch
in each Cell”, ISSCC Digest of Technical Papers, PP. 128-129, Feb.
2000.
[4] S. Tehrani, B. Engel, J. M. Slaughter, E. Chen, M. DeHerrera,
M. Durlam, P. Naji, R. Whig, J. Janesky, and J. Calder, “Recent
Developments in Magnetic Tunnel Junction MRAM”, IEEE Trans.
on Magnetics, Sept. 2000.
A 1Mbit MRAM has been demonstrated in a
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