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參數(shù)資料
| 型號(hào)： | VSLI2002_1MB_MRAM |
| 英文描述： | A low power 1Mbit MRAM based on 1T1MTJ bit cell integration with copper interconnects |
| 中文描述： | 甲低功耗1Mbit的基礎(chǔ)上1T1MTJ的MRAM位單元集成銅互連 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 246K |
| 代理商： | VSLI2002_1MB_MRAM |
To be published at VLSI Symposium 2002
Rmin)/Rmin) is critical for high-speed read circuitry. We
have been able to achieve MR signals over 45% at low bias
and over 30% at operating voltage with wafer uniformity
better than 1%. Another key element in the memory circuitry
is the reference cell. In our 1Mb architecture, we have
utilized a new concept for the reference cell. The reference
cell in the 1Mb circuit generates a signal that is mid-way
between the Rmax and Rmin resistance states of the MTJ (see
Fig. 6). The reference generator block is composed of a
column of mid-point reference cells located in the middle of
each 32kb block as seen in Fig. 7. Each mid-point reference
generator is composed of 4 MTJ devices in a series-parallel
combination. A MTJ device pair connected in series is
additionally connected in parallel with another series device
pair. The series device pairs are programmed such that one
device in the pair is anti-parallel and the other device is
parallel resulting in a resistive high and low state for the two
MTJ cells. The resulting series/parallel resistance
combination is a resistance that is (Rmax + Rmin) or mid-
way between Rmax and Rmin. The mid-point generator
improves matching between the target cells and the reference
due to the close proximity and the additional averaging of the
4MTJ reference cell. The averaging and close proximity
MRAM 32Kb Memory Block with Mid-Point Reference Generator
enables the mid-point generator to closely track the active
elements and to account for variations in processing.
6
7
8
9
10
11
12
13
14
-0.5 -0.4 -0.3 -0.2 -0.1
0
0.1
0.2
0.3
0.4
0.5
Midpt gen
Calc Midpt
Rmax
Rmin
Rmid
Bias Voltage (V)
R
-
μ
m
2
)
Fig. 6. Measured minimum, maximum and middle resistance
and calculated middle resistance curves vs. bias for a
midpoint generator reference cell.
R
max
R
min
Memory block - 1024X16
Generator
1/2*(Rmax+Rmin)
and Differential Amp
BL31
BL30
BL17
BL16
Memory block - 1024X16
R
max
R
min
BL0
BL1
BL14
BL15
Midpoint Reference
(Rmax+Rmin)//(Rmax+Rmin)=
Current Conveyors
Fig. 7. MRAM memory core block with mid-point reference generator circuitry.
1Mb MRAM
The 1Mb MRAM circuit (shown in Fig. 8) is a
demonstration vehicle for the development of the MRAM
technology. The circuit has onboard bias, reference, and
clock generation subcircuits, so no external reference
voltage, bias voltage, or clock signal is required. There are
three modes available: active, sleep, and standby. Active
mode has full power consumption and the circuit is ready
for random access. In sleep mode, random access and
other functions are disabled, but power consumption is
reduced. There is no power-up procedure required from
sleep mode to active mode. There is almost no power
consumption when the chip is in standby mode, but a
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