參數(shù)資料
型號(hào): VSC7135
廠商: Vitesse Semiconductor Corporation.
英文描述: 1.25Gbits/sec Gigabit Ethernet Transceiver
中文描述: 1.25Gbits/sec千兆以太網(wǎng)收發(fā)器
文件頁數(shù): 6/16頁
文件大?。?/td> 138K
代理商: VSC7135
VITESSE
Data Sheet
VSC7135
1.25Gbits/sec
Gigabit Ethernet Transceiver
Page 6
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
5/28/98
G52146-0, Rev. 4.0
Figure 5: Receive Timing Waveforms
Table 2: Receive AC Characteristics
Parameters
Description
Min.
Max.
Units
Conditions
T
1
Data or COM_DET Valid
prior to RCLK/RCLKN
rise
Data or COM_DET Valid
after RCLK or RCLKN
rise
Deviation of RCLK
rising edge to RCLKN
rising edge delay from
nominal.
f
10
3.0
ns.
Measured between the 1.4V
point of RCLK or RCLKN
and a valid level of R0:9. All
outputs driving 10pF load.
T
2
2.0
ns.
T
3
-500
500
ps.
Nominal delay is 10 bit times.
Tested on sample basis
T
4
Deviation of RCLK,
RCLKN frequency from
nominal.
f
----------------------
=
-1.0
1.0
%
Whether or not locked to
serial data
T
R
, T
F
R0:9, COM_DET, RCLK,
RCLKN rise and fall time
2.4
ns.
Between V
into 10 pf. load.
bc = Bit clock
ns = Nano second
8B/10B IDLE pattern.
Tested on a sample basis
IEEE 802.3Z Clause 38.68,
tested on a sample basis
IEEE 802.3Z Clause 38.69,
tested on a sample basis
il(max)
and V
ih(min)
,
R
lat
Latency from RX to R0:9
15bc + 2ns
34bc + 2ns
T
LOCK
Data acquisition lock time
@ 1.25 Gb/s
Total receive data jitter
tolerance (p-p)
Total deterministic data
jitter tolerance (p-p)
2.0
μ
s.
T
jtd
599
ps
D
jtd
370
ps
RCLK
R0:9
RCLKN
T
2
T
3
Data Valid
Data Valid
T
1
T
4
Data Valid
delay
-------------
T
3
±
=
f
RCLK
2
T
4
±
NOTE: Probability of Recovery for data acquisition is 95% per section 5.3 of the FC-PH rev. 4.3.
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