參數(shù)資料
型號: VSC7135
廠商: Vitesse Semiconductor Corporation.
英文描述: 1.25Gbits/sec Gigabit Ethernet Transceiver
中文描述: 1.25Gbits/sec千兆以太網(wǎng)收發(fā)器
文件頁數(shù): 1/16頁
文件大小: 138K
代理商: VSC7135
VITESSE
SEMICONDUCTOR CORPORATION
Page 1
5/28/98
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
Data Sheet
VSC7135
1.25Gbits/sec
Gigabit Ethernet Transceiver
G52146-0, Rev. 4.0
Features
General Description
The VSC7135 is a 1.25Gb/s Ethernet Transceiver optimized for Gigabit Ethernet or 1000Base-X applica-
tions. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes it
onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency. The VSC7135
also samples serial receive data on the RX PECL differential inputs, recovers the clock and data, deserializes it
onto the 10-bit receive data bus, outputs two recovered clocks at one-twentieth of the incoming baud rate and
detects “Comma” characters. The VSC7135 contains on-chip PLL circuitry for synthesis of the baud-rate trans-
mit clock, and extraction of the clock from the received serial stream. These circuits are fully monolithic and
require no external components.
VSC7135 Block Diagram
Gigabit Ethernet Transceiver @ 1.25Gb/s
Compliant to IEEE 802.3Z PMA
TTL Interface Compatible to PMA-TBI
Monolithic Clock Synthesis and Clock
Recovery - No External Components
125MHz TTL Reference Clock
Low Power Operation - 700 mW
Suitable for Both Coaxial or Optical Link
Applications
64 Pin, 14mm or 10mm Standard PQFP
Single +3.3V Supply
RX+
RX-
Q D
Serial to
Parallel
Clock
Recovery
Retimed
Data
÷
10
Recovered
Clock
Comma
Detect
Q D
R0:9
Frame
Logic
COM_DET
EN_CDET
T0:9
PLL Clock
Multiply
D Q
Parallel
to Serial
Serial Data
Synthesized
Clock
D Q
TX+
TX-
EWRAP
÷
20
RCLK
Resync
10
10
REFCLK
2:1
RCLKN
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