參數(shù)資料
型號(hào)： VSC7133QU
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 網(wǎng)絡(luò)接口
英文描述： 10-bit Transceiver for Fibre Channel and Gigabit Ethernet
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝： 10 MM, THERMALLY ENHANCED, PLASTIC, QFP-64
文件頁(yè)數(shù)： 14/18頁(yè)
文件大?。?/td> 304K
代理商： VSC7133QU
VITESSE
Advance Product Information
VSC7133
10-bit Transceiver for Fibre
Channel and Gigabit Ethernet
Page 14
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
1/17/00
G52187-0 Rev. 2.4
22
23
REFCLKP
REFCLKN
INPUT - Differential PECL or Single-Ended TTL
This rising edge of this clock latches T(0:9) into the input register. It also provides
the reference clock, at one tenth the baud rate to the PLL. If TTL, connect to
REFCLKP but leave REFCLKN open. If PECL, connect both REFCLKP and
REFCLKN.
62, 61
TX+, TX-
OUTPUTS - Differential PECL (AC Coupling recommended)
These pins output the serialized transmit data when EWRAP is LOW. When
EWRAP is HIGH, TX+ is HIGH and TX- is LOW.
45,44,43,41
40,39,38,36
35,34
R0,R1,R2,R3
R4,R5,R6,R7
R8,R9
OUTPUTS - TTL
10-bit received character. Parallel data on this bus is clocked out on the rising edges
of RCLK and RCLKN. R0 is the first bit received on RX+/RX-.
19
EWRAP
INPUT - TTL
LOW for Normal Operation. When HIGH, an internal loopback path from the
transmitter to the receiver is enabled and the TX outputs are held HIGH.
54, 52
RX+, RX-
INPUTS - Differential PECL (AC Coupling recommended)
The serial receive data inputs selected when EWRAP is LOW. Internally biased to
VDD/2, with 3.3K
resistors from each input pin to VDD and GND.
31, 30
RCLK,
RCLKN
OUTPUT - Complementary TTL
Recovered clocks derived from one twentieth of the RX+/- data stream. Each
rising transition of RCLK or RCLKN corresponds to a new word on R(0:9).
24
ENCDET
INPUT - TTL
Enables COMDET and word resynchronization when HIGH. When LOW, keeps
current word alignment and disables COMDET.
47
COMDET
OUTPUT - TTL
This output goes HIGH for half of an RCLK period to indicate that R(0:9) contains
a Comma Character (‘0011111XXX’). COMDET will go HIGH only during a
cycle when RCLKN is rising. COMDET is enabled by ENCDET being HIGH.
26
SIGDET
OUTPUT - TTL
SIGnal DETect. This output goes HIGH when the RX input contains a valid Fibre
Channel or Gigabit Ethernet signal. A LOW indicates an invalid signal.
16, 17
CAP0, CAP1
ANALOG: Differential capacitor for the CMU’s VCO. 0.1 uF nominal.
49
TCK
INPUT - TTL: JTAG clock input. Not normally connected.
48
TDI
INPUT - TTL: JTAG data input. Not normally connected.
55
TMS
INPUT - TTL: JTAG mode select input. Normally tied to V
DDD
INPUT - TLL: JTAG reset input. Tie to V
SSD
for normal operation.
OUTPU - TTL: JTAG data output. Normally tri-stated.
56
TRSTN
27
TDO
18
VDDA
Analog Power Supply.
Table 5: Pin Identification
Pin #
Name
Description
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VSC7135 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:1.25Gbits/sec Gigabit Ethernet Transceiver
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VSC7135QU 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver
VSC7139 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Quad Transceiver for Gigabit Ethernet and Fibre Channel
VSC7139TW 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm
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