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參數資料
| 型號： | VP16256-40CGGH1N |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Programmable FIR Filter |
| 中文描述： | 可編程FIR濾波器 |
| 文件頁數： | 8/20頁 |
| 文件大?。?/td> | 228K |
| 代理商： | VP16256-40CGGH1N |
8
VP16256
FILTER ACCURACY
Input data and coefficients are both represented by 16-bit
two’s complement numbers. The coefficients are converted to
twelve bits by rounding towards zero. This is achieved as
follows. If the coefficient is positive then the least significant
4 bits are discarded. If the coefficient is negative then the
logical ‘OR’ of the least significant 4 bits are added to the
remainder of the word. Twelve bit coefficients can be used
directly provided the least significant four bits are set to zero.
The FIR filter results are calculated using a multiplier
accumulator structure as shown in Fig. 9. The truncation and
word growth allowed for in the data path are explained in
Fig.10. The 16-bit data and 12-bit coefficient inputs (each with
one sign bit before the binary point), are presented to the
multiplier. This produces a 28-bit result with two bits before the
binary point. Producing the full 28-bit result ensures that if both
the data and coefficients are set to logic 1 a valid result is
generated. Prior to entering the accumulator the least
significant 4 bits of the multiplier result are truncated and the
resulting 24 bits sign extended to 32 bits. The final accumulator
result is 32 bits with 10 bits before the binary point. Thus 9 bits
of word growth are allowed within the accumulator. All
accumulator bits are made available on the output pins.
In cascade mode the middle 16 bits from the network A
accumulator are fed round to the network B data inputs, see
Fig. 10.
COEFFICIENT
ADDER
INPUT DATA
ACCUMULATOR
RESULT
S
8
7
6
5
4
3
2
1
0
S
S
S
S
S
S
S
S
S
0
S
0
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26
S
S
ACCUMULATOR RESULT
These bits are passed to filter network B during cascade mode
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25
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24
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23
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22
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14
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13
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12
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11
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10
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9
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8
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7
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6
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5
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4
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3
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2
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1
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22
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14
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13
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12
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11
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10
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9
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8
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7
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6
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5
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4
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3
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2
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1
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22
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14
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13
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12
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11
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10
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9
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8
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7
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6
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5
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4
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3
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2
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1
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11
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10
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9
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8
-
7
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6
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5
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4
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3
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2
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1
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14
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13
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12
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11
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10
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9
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8
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6
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5
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4
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3
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2
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1
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15
ACCUMULATOR RESULT
MULTIPLIER RESULT
COEFFICIENT
INPUT DATA
Sign extended to 32 bits, least significant 4 bits truncated
Multiplication producing a 28-bit result
Fig. 10 Filter accuracy
Fig. 9 Multiplier Accumulator
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相關代理商/技術參數 |
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| VP165/24 | 制造商:Smarteq Wireless Ab 功能描述: |
| VP166-144KR-00000 | 制造商:Carling Technologies 功能描述:V-SERIES ILLUMINATED PLUG - Bulk |
| VP166-155EE-00000 | 制造商:Carling Technologies 功能描述:V-SERIES ILLUMINATED PLUG - Bulk |
| VP166-155KK-00000 | 制造商:Carling Technologies 功能描述:V-SERIES ILLUMINATED PLUG - Bulk |
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