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參數(shù)資料
| 型號(hào)： | VP16256-40CGGH1N |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Programmable FIR Filter |
| 中文描述： | 可編程FIR濾波器 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 228K |
| 代理商： | VP16256-40CGGH1N |
11
VP16256
swap on every data sampling clock. This function does not
depend on the status of SWAP or bit, and the lower bank will be
initially selected after FEN goes active. The option can be used
to implement filters with complex coefficients.
LOADING COEFFICIENTS
When the device is to operate in a stand alone application
then the coefficients can be down loaded as a complete set from
a previously programmed EPROM. Alternatively if the system
contains a microprocessor they can be individually transferred
from a remote master under software control. In any mode the
system clock must be present and stable during the transfer, and
the addressing scheme is such that the least significant address
specifies the coefficient applied to the first multiplier seen by
incoming data.
The addresses used during the load operation are those
illustrated in Fig. 13. The Control Register is loaded when CCS
is high. In byte mode address A0 is used to select the portion of
control register loaded, otherwise the address bits are redundant.
When an EPROM is used to provide coefficients, this redundancy
causes the number of locations needed for any device to be
double that for the coefficients alone.
AUTO EPROM LOAD
When EPROM is tied low, the VP16256 assumes the role of
a master device in the system and controls the loading of
coefficients from an external EPROM, see Fig.15. A load
sequence commences when the RES input goes high, and will
continue until every coefficient has been loaded. BUSY goes high
to indicate that a load sequence is occurring and the filter output
is invalid. The device will not commence a filter operation until the
FEN edge is received after BUSY has gone low. This requirement
can be avoided if FRUN is tied high.
The address bus pins become outputs on the Master device,
and produce a new address every four system clock periods. This
four clock interval, minus output delays and the data set up time,
defines the available EPROM access time.
The coefficients are always loaded as bytes. The state of the
BYTE pin on the master device is ignored. This arrangement also
allows the eight most significant coefficient bus pins (C15:8) to be
used for other purposes as described later. Since the 16-bit
coefficients are loaded in two bytes the A0 pin specifies the
required byte. The maximum number of stored coefficients is
128, eight address outputs are therefore provided for the
EPROM. These eight outputs from the Master must also drive the
address inputs on the slave devices.
LOAD LAST
MASTER
COEFFICIENT
SCLK
A7:0
CCS
C15:12
FE
FF
00
01
00
01
FE
FF
00
01
00
01
0000
0001
0001
0010
LOAD SLAVE 1
CONTROL
REGISTER
LOAD SLAVE 1
COEFFICIENTS
LOAD LAST
SLAVE 1
COEFFICIENT
LOAD SLAVE 2
CONTROL
REGISTER
LOAD SLAVE 2
COEFFICIENTS
Fig. 14a EPROM load sequence
Fig. 14b EPROM load sequence for a cascaded system
SCLK
00
01
00
LOAD MASTER CONTROL
REGISTER
LOAD LAST COEFFICIENT
A7:0
00
01
LOAD FIRST COEFFICIENT
VALID ADDR
VALID ADDR
CCS
RES
BUSY
Fig. 14 EPROM load sequence timing diagrams
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VP16256 | Programmable FIR Filter |
| VP16256-27 | Programmable FIR Filter |
| VP16256-27CG | Programmable FIR Filter |
| VP16256-40CG | Programmable FIR Filter |
| VP16256-27CGGH1N | Programmable FIR Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VP16256-40CGGH1R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
| VP165/24 | 制造商:Smarteq Wireless Ab 功能描述: |
| VP166-144KR-00000 | 制造商:Carling Technologies 功能描述:V-SERIES ILLUMINATED PLUG - Bulk |
| VP166-155EE-00000 | 制造商:Carling Technologies 功能描述:V-SERIES ILLUMINATED PLUG - Bulk |
| VP166-155KK-00000 | 制造商:Carling Technologies 功能描述:V-SERIES ILLUMINATED PLUG - Bulk |
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