參數(shù)資料
型號： VNC2-64Q1B-REEL
廠商： FTDI, Future Technology Devices International Ltd
文件頁數(shù)： 55/88頁
文件大小： 0K
描述： IC USB HOST/DEVICE CTRL 64-QFN
應(yīng)用說明： Vinculum-II IO Cell Description AppNote
Vinculum-II Debug Interface Description AppNote
Vinculum-II IO Mux Explained AppNote
Vinculum-II PWM Example AppNote
Migrating Vinculum Designs AppNote
特色產(chǎn)品： Vinculum VNC2
標(biāo)準(zhǔn)包裝： 1
系列： Vinculum-II
控制器類型： USB 2.0 控制器
接口： USB，主機(jī)/設(shè)備配置，UART，SPI，PWM，閃存 256K，DMA 4CH
電源電壓： 1.62 V ~ 1.98 V
電流 - 電源： 25mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-QFN（8x8）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 634 (CN2011-ZH PDF)
其它名稱： 768-1046-6
59
Copyright 2009-2011 Future Technology Devices International Limited
Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.5
Document No.: FT_000138 Clearance No.: FTDI# 143
64 Pin
Package
Available
pins
48 Pin
Package
Available
pins
32 Pin
Package
Available
pins
Name
Type
Description
12, 16,
20, 25,
29, 40,
44, 48,
52, 58,
62
12,16,
21, 32,
36, 42,
46
12, 24,
30
fifo_txe#
Output
When high, do not write data into the FIFO.
When low, data can be written into the FIFO
by strobing fifo_wr# high, then low.
13, 17,
22, 26,
31, 41,
45, 49,
55, 59,
63
13, 18,
22, 33,
37, 43,
47
14, 25,
31
fifo_rd#
Input
Enables the current FIFO data byte on
D0...D7 when low. Fetches the next FIFO
data byte (if available) from the receive
FIFO buffer when fifo_rd# goes from high to
low
14, 18,
23, 27,
32, 42,
46, 50,
56, 60,
64
14, 19,
23, 34,
38, 44,
48
15, 26,
32
fifo_wr#
Input
Writes the data byte on the D0...D7 pins
into the transmit FIFO buffer when fifo_wr#
goes from high to low.
Table 6.16 Data and Control Bus Signal Mode Options - Parallel FIFO Interface
6.6.2 Read / Write Transaction Asynchronous FIFO Mode
When in Asynchronous FIFO interface mode, the timing of read and write operations on the FIFO
interface are shown in Figure 6.22 and Table 6.17.
In asynchronous mode an external device can control data transfer driving FIFO_WR# and FIFO_RD#
inputs. In contrast to synchronous mode, in asynchronous mode the 245 FIFO module generates the
output enable EN# signal. EN# signal is effectively the read signal RD#.
Current byte is available to be read when FIFO_RD# goes low. When FIFO_RD# goes high, FIFO_RXF#
output will also go high. It will only become low again when there is another byte to read.
When FIFO_WR# goes low FIFO_TXE# flag will always go high. FIFO_TXE# goes low again only when
there is still space for data to be written in to the module.
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