參數(shù)資料
型號： VNC2-64Q1B-REEL
廠商： FTDI, Future Technology Devices International Ltd
文件頁數(shù)： 35/88頁
文件大?。?/td> 0K
描述： IC USB HOST/DEVICE CTRL 64-QFN
應(yīng)用說明： Vinculum-II IO Cell Description AppNote
Vinculum-II Debug Interface Description AppNote
Vinculum-II IO Mux Explained AppNote
Vinculum-II PWM Example AppNote
Migrating Vinculum Designs AppNote
特色產(chǎn)品： Vinculum VNC2
標(biāo)準(zhǔn)包裝： 1
系列： Vinculum-II
控制器類型： USB 2.0 控制器
接口： USB，主機(jī)/設(shè)備配置，UART，SPI，PWM，閃存 256K，DMA 4CH
電源電壓： 1.62 V ~ 1.98 V
電流 - 電源： 25mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-QFN（8x8）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 634 (CN2011-ZH PDF)
其它名稱： 768-1046-6
40
Copyright 2009-2011 Future Technology Devices International Limited
Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.5
Document No.: FT_000138 Clearance No.: FTDI# 143
Mode
Pins
Word Size
Handshaking
Speed
Comments
VNC1L
4
12
Yes
Read 66%
Write 66%
Legacy mode
Full Duplex
4
8
Yes
Read 50%
Write 100%
Half Duplex 4 pin
4
8
Yes
Read 100%
Write 100%
MOSI becomes
bi-directional
Half Duplex 3 pin
3
8
Yes
Read 50%
Write 50%
MOSI becomes
bi-directional
Unmanaged
4
8
No
Read 100%
Write 100%
Table 6.3 - SPI Slave Speeds
VNC2 SPI Master is described in Section 6.4.1 SPI Master Signal Descriptions.
Table 6.5 shows the SPI master signals and the available pins that they can be mapped to depending on
the package size. Further details on the configuration of input and output signals are available in Section
6.2.1 SPI Clock Phase Modes
SPI interface has 4 unique modes of clock phase (CPHA) and clock polarity (CPOL), known
as Mode 0, Mode 1, Mode 2 and Mode 3. Table 6.4 summarizes these modes and available interface and
Figure 6.3 is the function timing diagram.
For CPOL = 0, the base (inactive) level of SCLK is 0.
In this mode:
When CPHA = 0, data is clocked in on the rising edge of SCLK, and data is clocked out on the
falling edge of SCLK.
When CPHA = 1, data is clocked in on the falling edge of SCLK, and data is clocked out on the
rising edge of SCLK
For CPOL =1, the base (inactive) level of SCLK is 1.
In this mode:
When CPHA = 0, data v in on the falling edge of SCLK, and data is clocked out on the rising edge
of SCLK
When CPHA =1, data is clocked in on the rising edge of SCLK, and data is clocked out on the
falling edge of SCLK.
Mode
CPOL
CPHA
Full
Duplex
Half
Duplex
4 pin
Half
Duplex
3 pin
Unmanged
VNC1L
Legacy
0
N
Y
N
1
0
1
Y
N
2
1
0
N
Y
N
3
1
Y
N
Table 6.4 - Clock Phase/Polarity Modes
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