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參數(shù)資料
| 型號(hào)： | VES9600 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single Chip DVB-T Channel Receiver(單片DVB-T頻道接收器) |
| 中文描述： | 單芯片DVB - T信道接收器（單片的DVB - T頻道接收器） |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 107K |
| 代理商： | VES9600 |
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1999 Sep 01
6
Philips Semiconductors
Product specification
Single Chip DVB-T Channel Receiver
VES9600
from the voltage on pin VREF through an on-chip fully-differential
amplifier. The voltage on this pin is nominally equal to CMO + 0.25
volts.
This is the negative voltage reference for the A/D converter. It is
derived from the voltage on pin VREF through an on-chip fully-
differential amplifier. The voltage on this pin is nominally equal to
CMO- 0.25 volts.
Power supply input for the digital switching circuitry (3.3 typ).
Ground return for the digital switching circuitry.
Power supply input for the analog clock drivers (3.3V typ).
Ground return for the analog clock drivers.
Power supply input for the analog circuits (3.3V typ).
Ground return for analog circuits.
Power supply input that connects to an n-well guard ring that
surrounds the ADC (3.3V typ).
Ground return for the well guard ring that surrounds the ADC.
VREFM
43
O
VD1
VS1
VD2
VS2
VD3
VS3
38
37
51
50
46
47
52
I
I
I
I
I
I
VD4
I
VS4
36
I
I2C INTERFACES
I2C serial clock. Up to 700 kbit/s, in this functional mode, I2C slave
device
I2C serial data inout, open drain I/O pad Up to 700 kbit/s, in this
functional mode, I2C slave device
SADDR[1:0] are the 2 LSBs of the I2C address of the VES9600. The
MSBs are internally set to 00010. Therefore the complete I2C address
of the VES9600 is (MSB to LSB): 0,0,0,1,0,SADDR[1], SADDR[0]
tuner I2C serial clock signal. Can be connected or not to the master
I2C bus. (open drain)
Tuner I2C data bus. Can be connected or not to the master I2C bus.
(open drain)
Extra I2C clock line to download DSP code from an external
EEPROM. Optional mode. Can be connected to the master I2C Bus
, (open drain)
Extra I2C data bus to download DSP code from an external EEPROM.
Optional mode. Can be connected to the master I2C Bus. (open drain)
SCL
62
I
SDA
63
I/O
SADDR[1:0]
206-207
I
SCL_TUN
64
O
SDA_TUN
65
I/O
SCL_EEP
66
O
SDA_EEP
67
I/O
EEPADDR[1:0]
204-205
I
EEPRAD[1:0] are the 2 LSBs of the I2C address of the EEPROM in
mode boot alone. The MSBs are internally set to 00010. Therefore the
complete I2C address of the EEPROM is (MSB to LSB):
1,0,1,0,0,EEPADDR[1], EEPADDR[0]
I2C EEPROM bus speed (SCL_EEP) :
0 : 800Khz; 1 : 400Khz; 2 : 200Khz; 3 : 100Khz.
EEPSP[1:0]
202-203
I
DSP SIGNALS
DOWNLOAD_M
ODE
4
I
processor control, Boot Mode
If 0 the DSP download its software from an external eeprom on the
dedicated I2C BUS SDA_EEP and SCL_EEP.
If 1 the software is downloaded via a host in the I2C register
CODE_IN. In this case no need of an external eeprom.
Boot on the bist mode to test the DSP RAM bank.
If good SP_OUT[0] = 1
In normal mode of operation, DSP_BIST must be grounded.
Oak+ DSP smart debug interface, SDI+ external JTAG clock
Oak+ DSP smart debug interface, SDI+ JTAG serial output
Oak+ DSP smart debug interface, SDI+ JTAG test mode select
Oak+ DSP smart debug interface, SDI+ JTAG serial output
DSP_BIST
3
I
SDI_TCK
SDI_TDI
SDI_TMS
SDI_TDO
194
195
196
197
I
I
I
O
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