參數(shù)資料
型號(hào): VES9600
廠商: NXP Semiconductors N.V.
英文描述: Single Chip DVB-T Channel Receiver(單片DVB-T頻道接收器)
中文描述: 單芯片DVB - T信道接收器(單片的DVB - T頻道接收器)
文件頁(yè)數(shù): 2/16頁(yè)
文件大小: 107K
代理商: VES9600
1999 Sep 01
2
Philips Semiconductors
Product specification
Single Chip DVB-T Channel Receiver
VES9600
FEATURES
2K and 8K COFDM demodulator ( Fully
DVB-T compliant : ETS 300-744).
All modes supported including
hierarchical modes.
On chip 9-bit ADC.
Digital down conversion.
Fully automatic transmission parameters
detection.
Crystal or VCXO clock generation.
Frequency offset estimator to speed up
the scan.
RF Tuner input power measurement
On chip FEC decoder, full DVB-T
compliant.
Parallel or serial transport stream
interface.
DSP based synchronization.
BER measurement
SNR estimation
Channel frequency response output.
Channel impulse response output.
Controllable dedicated I2C tuner bus.
2 low frequency spare DAC. (
Σ
)
Spare I/O.
I2C bus interface, for easy control.
CMOS 0.35
μ
m technology.
APPLICATIONS
DVB-T fully compatible.
Digital data transmission using
COFDM modulations.
DESCRIPTION
The VES9600 is a single chip channel receiver for 2K and 8K
COFDM modulated signals based on the ETSI specification (ETSI
300 744). The device interfaces directly to an IF signal, which is
sampled by a 9-bit AD converter.
The VES9600 performs all the COFDM demodulation tasks from IF
signal to the MPEG2 transport stream. An internal DSP core
manages the synchronization and the control of the demodulation
process.
After base band conversion and FFT, the channel frequency
response is estimated based on the scattered pilots, and filtered in
both time and frequency domains. This estimation is used as a
correction on the signal, carrier by carrier. A common phase error
and estimator is used to deal with the tuner phase noise.
The FEC decoder is automatically synchronized thanks to the frame
synchronization algorithm that uses the TPS information included in
the modulation. Finally descrambling according to DVB-T standard,
is achieved at the Reed Solomon output.
This device is controlled via an I2C bus. The chip provides a
switchable tuner I2C bus to be disconnected from the I2C master
when not necessary. The DSP software code can be fed to the
chip via the master I2C bus or via a dedicated I2C bus (Eeprom).
Designed in 0.35
μ
m CMOS technology and housed in a 208-pin
MQFP package, the VES9600 operates over the commercial
temperature range.
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