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參數(shù)資料
| 型號： | VES9600 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single Chip DVB-T Channel Receiver(單片DVB-T頻道接收器) |
| 中文描述： | 單芯片DVB - T信道接收器（單片的DVB - T頻道接收器） |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 107K |
| 代理商： | VES9600 |
1999 Sep 01
5
Philips Semiconductors
Product specification
Single Chip DVB-T Channel Receiver
VES9600
IT
76
O
(5V)
Interrupt line. This output interrupt line can be configured by the I2C
interface. See registers Itsel and Itstat. IT is an open drain output and
therefore requires an external pull up resistor.
FEC OUTPUTS
output data carrying the current sample of the current MPEG2 packet
(188 bytes), delivered on the rising edge of OCLK by default. When
the serial mode is selected, the output data is delivered by DO[0].
Output CLock. OCLK is the output clock for the parallel DO[7:0]
outputs. OCLK is internally generated depending on which interface is
selected.
output data validation signal active high during the valid and regular
data bytes (may be inverted, see serial bus description).
Pulse SYNChro. This output signal goes high on a rising edge of
OCLK when a synchro byte is provided, then goes low until the next
synchro byte (may be inverted).
RS error flag, active high on one RS packet if the RS decoder fails in
correcting the errors (may be inverted).
Frame start active high for one OCLK output clock cycle at the
beginning of a new superframe made of 272 OFDM symbols for the 2k
mode and made of 68 OFDM symbols for the 8k mode (may be
inverted as C3_psync).
viterbi output data stream, delivered on the rising hedge of HVIT. You
can also find the viterbi output on DO[0] after by-passing the RS and
the descrambling.
DO[7:0]
118-119-120-
121-124-125-
126-127
113
O
(3.3)
OCLK
O
(3.3)
DEN
115
O
(3.3)
O
(3.3)
PSYNC
112
UNCOR
114
O
(3.3)
O
(3.3)
FSTART
109
DVIT
108
O
(3.3)
HVIT
107
O
(3.3)
viterbi output data stream clock, according to DVIT.
ON-CHIP ADC SIGNALS
Negative input to the A/D converter. This pin is DC biased to half
supply through an internal resistor divider (2x10K resistors). In order
to remain in the range of the ADC, the voltage difference between pins
VIP and VIM should be between -0.5 and 0.5 volts.
Positive input to the A/D converter. This pin is DC biased to half supply
through an internal resistor divider (2x10K resistors). In order to
remain in the range of the ADC, the voltage difference between pins
VIP and VIM should be between –0.5 and 0.5 volts.
This pin is connected to a tap point on an internal resistor divider used
to create CMO and CMI. An external capacitor of value 0.1
μ
f should
be connected between this point and ground to provide good power
supply rejection from the positive supply at higher frequencies.
An external resistor of value 3.3k should be connected between this
pin and ground to provide good accurate bias currents for the analog
circuits on the ADC.
This pin provides the common-mode in voltage for the analog circuits
on the ADC. It is the buffered version of a voltage derived from an on-
chip resistor devider, and has a nominal value of 0.75 x VD3.
This pin provides the common-mode out voltage for the analog circuits
on the ADC. It is the buffered version of a voltage derived from an on-
chip resistor devider, and has a nominal value of 0.5 x VD3.
This is the output of an on-chip resistor divider. An external capacitor
of value 0.1
μ
f should be connected between this point and ground to
provide good power supply rejection from the positive supply at higher
frequencies. Reference voltages VREFP and VREFM are derived from
the voltage on VREF.
This is a positive voltage reference for the A/D converter. It is derived
VIM
48
I
VIP
49
I
CMCAP
42
I
RBIAS
39
I
CMI
40
O
CMO
41
O
VREF
45
O
VREFP
44
O
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