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參數(shù)資料
| 型號： | VDP31XXB |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video Processor Family |
| 中文描述： | 視頻處理器系列 |
| 文件頁數(shù)： | 51/72頁 |
| 文件大?。?/td> | 597K |
| 代理商： | VDP31XXB |
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PRELIMINARY DATA SHEET
VDP 31xxB
51
Micronas
Pin 41, 42, 43, 45, 46, 47
–
Analog RGB Inputs,
RIN1/2,
GIN1/2, BIN1/2
(Fig. 4
–
15)
These pins are used to insert an external analog RGB
signal, e.g. from a SCART connector which can by
switched to the analog RGB outputs with the fast blank
signal. The analog backend provides separate bright-
ness and contrast settings for the external analog RGB
signals.
Pin 44, 48
–
Fast Blank Inputs,
FBLIN1/2
(Fig. 4
–
15)
These pins are used to switch the RGB outputs to the ex-
ternal analog RGB inputs.
Pin 49
Main Clock Output,
CLK20
(Fig. 4
–
4)
This is the 20.25MHz main system clock, that is used by
all circuits in a high-end VDP system. All external timing
is derived from this clock.
Pin 50
–
Horizontal Drive Output,
HOUT
(Fig. 4
–
18)
This open drain output supplies the the drive pulse for
the horizontal output stage. The polarity and gating with
the flyback pulse are selectable by software.
Pin 51, 52
–
Crystal Input and Output,
XTAL1
,
XTAL2
(Fig. 4
–
7)
These pins are connected to an 20.25 MHz crystal oscil-
lator is digitally tuned by integrated shunt capacitances.
The Clk20 and Clk5 clock signals are derived from this
oscillator. An external clock can be fed into XTAL1. In
this case clock frequency adjustment must be switched
off.
Pin 53
–
Standby Supply Voltage,
VSTBY
In standby mode, only the clock oscillator and the hori-
zontal drive circuitry are active.
Pin 54
–
CCU 5 MHz Clock Output,
CLK5
(Fig. 4
–
10)
This pin provides a clock frequency for the TV microcon-
troller, e.g. a CCU3000 controller.
Pin 55
–
Ground (Analog Front-end),
GND
F
Pin 56
–
Ground (Analog Signal Input),
ISGND
(Fig. 4
–
8)
This is the high quality ground reference for the video
input signals.
Pin 57
–
Reference Voltage Top,
VRT
(Fig. 4
–
8)
Via this pin, the reference voltage for the A/D converters
is decoupled. The pin is connected with 10 F/47 nF to
the Signal Ground Pin.
Pin 58
–
Supply Voltage (Analog Front-end),
VSUP
F
Pin 59
–
Analog Video Output,
VOUT
(Fig. 4
–
6)
The analog video signal that is selected for the main
(luma, cvbs) adc is output at this pin. An emitter follower
is required at this pin.
Pin 60
–
Analog Chroma Input,
CIN
(Fig. 4
–
9)
This pin is connected to the S-VHS chroma signal. A re-
sistive divider is used to bias the input signal to the
middle of the converter input range. CIN can only be
connected to the chroma (Video 2) A/D converter. The
signal must be AC-coupled.
Pin 61...64
–
Analog Video Input 1
–
4,
VIN1
–
4
(Fig. 4
–
11)
These are the analog video inputs. A CVBS or S-VHS
luma signal is converted using the luma (Video 1) AD
converter. The input signal must be AC-coupled.
4.4. Pin Configuration
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Fig. 4
–
2:
64-pin PSDIP package
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