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參數(shù)資料
| 型號： | V58C3643204SAT |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 3.3 VOLT 2M X 32 DDR SDRAM 4 X 512K X 32 |
| 中文描述： | 高性能3.3伏200萬× 32 DDR SDRAM的4 × 512k × 32的 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 278K |
| 代理商： | V58C3643204SAT |
9
V58C3643204SAT Rev. 1.4 August 2001
MOSEL VITELIC
V58C3643204SAT
AC Characteristics
Parameter
Symbol
-45
-50
-55
-60
Unit
Min
Max
Min
Max
Min
Max
Min
Max
CK cycle time
CL=3
t
CK
7
5 .0
7
5.5
7
6 .0
7
ns
CL=4
4.5
ns
CK high level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
CK low level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
DQS out access time from CK
t
DQSCK
-0.70
+0.70
-0.70
+0.70
-0.75
+0.75
-0.75
+0.75
ns
Output access time from CK
t
AC
-0.70
+0.70
-0.70
+0.70
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to output data edge
t
DQSQ
-
0.5
-
0.5
-
0.5
ns
Read preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
Read postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
CK to valid DQS-in
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS-In setup time
t
WPRES
0
-
0
-
0
-
ns
DQS-in hold time
t
WPREH
0.25
-
0.25
-
0.25
-
t
CK
DQS write postamble
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
DQS-In high level width
t
DQSH
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
DQS-In low level width
t
DQSL
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
Address and Control input setup time
t
IS
1.2
-
1.2
-
1.2
-
ns
Address and Control input hold time
t
IH
0.9
-
0.9
-
0.9
-
ns
DQ and DM setup time to DQS
t
DS
0.5
-
0.5
-
0.5
-
ns
DQ and DM hold time to DQS
t
DH
0.5
-
0.5
-
0.5
-
ns
Clock half period
t
HP
t
CLmin
or
t
CHmin
-
t
CLmin
or
t
CHmin
-
t
CLmin
or
t
CHmin
-
ns
Output DQS valid window
t
QH
t
HP
-
0.75ns
-
t
HP
-
0.75ns
-
t
HP
-
0.75ns
-
ns
Row cycle time
t
RC
58
60
60.5
60
ns
Refresh row cycle time
t
RFC
69
70
71.5
72
ns
Row active time
t
RAS
40
100K
44
100K
48
100K
ns
RAS to CAS delay
t
RCD
18
20
22
24
ns
Row precharge time
t
RP
12
20
16.5
18
ns
Row active to Row active delay
t
RRD
9
14
11
12
ns
Last data in to Row precharge
t
WR
2
2
2
2
t
CK
Last data in to Read command delay
t
CDLR
2
2
2
2
t
CK
Col. address to Col. address delay
t
CCD
1
1
1
1
t
CK
Mode register set cycle time
t
MRD
2
2
2
2
t
CK
Power down exit time
t
PEDX
1t
CK
+t
IS
1t
CK
+t
IS
1t
CK
+t
IS
ns
Self refresh exit to active command delay
t
XSA
69
70
71.5
72
ns
Self refresh exit to read command delay
t
XSR
200
200
200
t
CK
Auto precharge write recovery +
Precharge
t
DAL
6
6
5
5
t
CK
Refresh interval time
t
REF
7.8
7.8
7.8
μs
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