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參數(shù)資料
| 型號： | V58C3643204SAT |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 3.3 VOLT 2M X 32 DDR SDRAM 4 X 512K X 32 |
| 中文描述： | 高性能3.3伏200萬× 32 DDR SDRAM的4 × 512k × 32的 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 278K |
| 代理商： | V58C3643204SAT |
7
V58C3643204SAT Rev. 1.4 August 2001
MOSEL VITELIC
V58C3643204SAT
Power & DC Operating Conditions (SSTL_2 In/Out)
Recommended operating conditions (Voltage referenced to V
SS
=0V, T
A
=0 to 65
°
C)
AC Input Operating Conditions
Recommended operating conditions
(Voltage referenced to V
SS
=0V, V
DD
=3.3V+ 5%, V
DDQ
=2.5V+ 5%, T
A
=0 to 65
°
C)
SSTL_2 AC Test Conditions
Notes:
1. Input waveform timing is referenced to the input signal crossing the V
level applied to the device.
2. Compliant devices must still meet the V
(AC) and V
(AC) specifications under actual use conditions.
3. The 1 V/ns input signal minimum slew rate is to be maintained in the V
IL
max (AC) to V
IL
min (AC) range of the input
signal swing.
Parameter
Symbol
Min
Typ
Max
Unit
Device Supply voltage
V
DD
3.135
3.3
3.465
V
Output Supply voltage
V
DDQ
2.375
2.50
2.625
V
Reference voltage
V
REF
0.49*V
DDQ
-
0.51*V
DDQ
V
Termination voltage
V
tt
V
REF
-0.04
VREF
V
REF
+0.04
V
Input logic high voltage
V
IH
V
REF
+0.15
-
V
DDQ
+0.30
V
Input logic low voltage
V
IL
-0.30
-
V
REF
-0.15
V
Output logic high voltage I
OH
= -15.2mA
V
OH
Vtt+0.76
-
-
V
Output logic low voltage
V
OL
-
-
Vtt-0.76
V
Input leakage current
I
IL
-5
-
5
μA
Output leakage current
I
OL
-5
-
5
μA
Parameter
Symbol
Min
Typ
Max
Unit
Input High (Logic 1) Voltage; DQ
V
IH
V
REF
+0.35
-
-
V
Input Low (Logic 0) Voltage; DQ
V
IL
-
-
V
REF
-0.35
V
Clock Input Differential Voltage; CK and CK
V
ID
0.7
-
V
DDQ
+0.6
V
Clock Input Crossing Point Voltage; CK and CK
V
IX
0.5*V
DDQ
-0.2
-
0.5*V
DDQ
+0.2
V
Symbol
Parameter
Value
Units
Notes
V
REF
Input Reference Voltage
0.5*V
DDQ
V
1
V
SWING
(max)
Input Signal Maximum Peak to Peak Swing
1.5
V
1, 2
SLEW
Input Signal Minimum Slew Rate
1.0
V/ns
3
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