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參數(shù)資料
| 型號(hào)： | V54C365404VELF6 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 4 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| 封裝： | LEAD FREE, MO-210, FBGA-60 |
| 文件頁(yè)數(shù)： | 9/54頁(yè) |
| 文件大?。?/td> | 694K |
| 代理商： | V54C365404VELF6 |
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17
V54C365(16/80/40)4VE Rev. 1.1 January 2005
ProMOS TECHNOLOGIES
V54C365(16/80/40)4VE
AC Characteristics 1,2, 3
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
#
Symbol
Parameter
Limit Values
Unit Note
-6
-7PC
-7
-8PC
Min. Max. Min. Max. Min. Max. Min. Max.
Clock and Clock Enable
1tCK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
6
7.5
–
7
7.5
–
7
10
–
8
10
–
s
ns
2tCK
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
166
133
–
143
133
–
143
100
–
125
100
MHz
3tAC
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
–
_
5.4
–
_
5.4
–
_
5.4
6
–
_
6
ns
2, 4
4tCH
Clock High Pulse Width
2.5
–
2.5
–
2.5
–3–ns
5tCL
Clock Low Pulse Width
2.5
–
2.5
–
2.5
–3–ns
6tT
Transition Tim
0.3
1.2
0.3
1.2
0.3
1.2
0.5
10
ns
Setup and Hold Times
7tIS
Input Setup Time
1.5
–
1.5
–
1.5
–2–ns
5
8tIH
Input Hold Time
0.8
–
0.8
–
0.8
–1–ns
5
9tCKS
Input Setup Time
1.5
–
1.5
–
1.5
–2–ns
5
10
tCKH
CKE Hold Time
0.8
–
0.8
–
0.8
–1–ns
5
11
tRSC
Mode Register Set-up Time
12
–
14
–
14
–
16
–
ns
12
tSB
Power Down Mode Entry Time
0
6
0
7
0
708ns
Common Parameters
13
tRCD
Row to Column Delay Time
12
–
15
–
15
–
20
–
ns
6
14
tRP
Row Precharge Time
15
–
15
–
15
–
20
–
ns
6
15
tRAS
Row Active Time
40
100K
42
100K
42
100K
45
100k
ns
6
16
tRC
Row Cycle Time
60
–
60
–
60
–
60
–
ns
6
17
tRRD
Activate(a) to Activate(b) Command Period
12
–
14
–
14
–
16
–
ns
6
18
tCCD
CAS(a) to CAS(b) Command Period
1
–
1
–
1
–
1
–
CLK
Refresh Cycle
19
tREF
Refresh Period (4096 cycles)
—
64
—
64
—
64
—
64
ms
20
tSREX
Self Refresh Exit Time
1
—
1
—
1
—
1
—
CLK
Read Cycle
21
tOH
Data Out Hold Time
2.5
–
3
–
3
–3–ns
2
22
tLZ
Data Out to Low Impedance Time
1
–
1
–
1
–0–ns
23
tHZ
Data Out to High Impedance Time
3
6
3
7
3
738ns
7
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