參數(shù)資料
型號(hào)： V54C365404VELF6
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 16M X 4 SYNCHRONOUS DRAM, 5.4 ns, PBGA60
封裝： LEAD FREE, MO-210, FBGA-60
文件頁(yè)數(shù)： 6/54頁(yè)
文件大?。?/td> 694K
代理商： V54C365404VELF6
ProMOS TECHNOLOGIES
V54C365(16/80/40)4VE
14
V54C365(16/80/40)4VE Rev. 1.1 January 2005
Burst Length and Sequence:
Burst
Length
Starting
Address
(A2 A1 A0)
Sequential Burst
Addressing
(decimal)
Interleave Burst
Addressing
(decimal)
2xx0
xx1
0, 1
1, 0
0, 1
1, 0
4x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
Full Page
nnn
Cn, Cn+1, Cn+2....
not supported
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-
RAS refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An
on-chip address counter increments the word and the bank addresses and no bank information is required
for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high
at a clock timing. The mode restores word line after the refresh and no external precharge command is nec-
essary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same
rule applies to any access command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS, CAS,
and CKE are low and WE is high at a clock timing. All of external control signals including the clock are dis-
abled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit com-
mand, at least one tRC delay is required prior to any access command.
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to “high” at a
clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable
Latency tDQZ ). It also provides a data mask function for writes. When DQM is activated, the write operation
at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks must be pre-
charged and the necessary Precharge delay (trp) must occur before the SDRAM can enter the Power Down
mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK
and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device
can’t remain in Power Down mode longer than the Refresh period (tref) of the device. Exit from this mode is
performed by taking CKE “high”. One clock delay is required for mode entry and exit.
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