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參數(shù)資料
| 型號： | V54C365404VELF6 |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 4 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| 封裝： | LEAD FREE, MO-210, FBGA-60 |
| 文件頁數(shù)： | 1/54頁 |
| 文件大?。?/td> | 694K |
| 代理商： | V54C365404VELF6 |
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V54C365(16/80/40)4VE
64Mbit SDRAM
3.3 VOLT, TSOP II / FBGA
4M X 16, 8M X 8, 16M X 4
V54C365(16/80/40)4VE Rev. 1.1 January 2005
67PC
78PC
System Frequency (fCK)
166 MHz
143 MHz
125 MHz
Clock Cycle Time (tCK3)
6 ns
7 ns
8 ns
Clock Access Time (tAC3) CAS Latency = 3
5.4 ns
6 ns
Clock Access Time (tAC2) CAS Latency = 2
5.4 ns
6 ns
Features
■ 4 banks x 1Mbit x 16 organization
■ 4 banks x 2Mbit x 8 organization
■ 4 banks x 4Mbit x 4 organization
■ High speed data transfer rates up to 166 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/64 ms
■ Available in 60-ball FBGA and 54 Pin TSOPII
■ LVTTL Interface
■ Single +3.3 V
±0.3 V Power Supply
Description
The V54C365(16/80/40)4VE is a four bank Syn-
chronous DRAM organized as 4 banks x 1Mbit x 16,
4 banks x 2Mbit x 8, or 4 banks x 4Mbit x 4. The
V54C365(16/80/40)4VE achieves high speed data
transfer rates up to 166 MHz by employing a chip
architecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T/S
6
7PC
7
8PC
Std.
L
0
°C to 70°C
Blank
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相關(guān)代理商/技術(shù)參數(shù) |
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| V54C365804VC | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 |
| V54C365804VD | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 143/133/125 MHz 3.3 VOLT 8M X 8 SYNCHRONOUS DRAM 4 BANKS X 2Mbit X 8 |
| V5-5/RK 4-0.3/0.3/0.3 | 制造商:TURCK Inc 功能描述:Cordset, Splitter, M12 Female Straight x 3, 4 Wire, 5m, PVC, Yellow, U0986-00 |
| V5-5/RK 4-1/1/1 | 制造商:TURCK Inc 功能描述:Cordset, Splitter, M12 Female Straight x 3, 4 Wire, 5m, PVC, Yellow, U-16415 |
| V5509 | 制造商:Assmann Electronics Inc 功能描述:Old Part V5509^ASSMANN |
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