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參數(shù)資料
| 型號： | V54C3128804VCLC7E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 8 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封裝： | FBGA-54 |
| 文件頁數(shù)： | 1/56頁 |
| 文件大?。?/td> | 681K |
| 代理商： | V54C3128804VCLC7E |
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V54C3128(16/80/40)4VC
128Mbit SDRAM
3.3 VOLT, TSOP II / BGA PACKAGE
8M X 16, 16M X 8, 32M X 4
V54C3128(16/80/40)4VC Rev. 1.1 October 2007
56
7PC
7
System Frequency (fCK)
200 MHz
166 MHz
143 MHz
Clock Cycle Time (tCK3)
6 ns
7 ns
Clock Access Time (tAC3) CAS Latency = 3
4.5 ns
5.4 ns
Clock Access Time (tAC2) CAS Latency = 2
4.5 ns
5.4 ns
6 ns
Features
■ 4 banks x 4Mbit x 16 organization
■ 4 banks x 8Mbit x 8 organization
■ 4 banks x16Mbit x 4 organization
■ High speed data transfer rates up to 166 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/64 ms
■ Available in 54 Pin TSOP II, 54 Ball BGA, 60 Ball
BGA
■ LVTTL Interface
■ Single +3.3 V
±0.3 V Power Supply
Description
The V54C3128(16/80/40)4VC is a four bank Syn-
chronous DRAM organized as 4 banks x 4Mbit x 16,
4 banks x 8Mbit x 8, or 4 banks x 16Mbit x 4. The
V54C3256(16/80/40)4VC achieves high speed data
transfer rates up to 200 MHz by employing a chip
architecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
200 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
J/K/I
5
6
7PC
7
Std.
L
0
°C to 70°C
Blank
-40
°C to 85°C
I
-40
°C to 125°C
E
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V54C3128804VS | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 |
| V54C3128804VT | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 |
| V54C316162 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162V | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162V-5 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
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