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參數(shù)資料
| 型號(hào)： | V54C3256404VDS8IPC |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 SYNCHRONOUS DRAM, 6 ns, PBGA60 |
| 封裝： | MO-210, FBGA-60 |
| 文件頁數(shù)： | 1/56頁 |
| 文件大?。?/td> | 728K |
| 代理商： | V54C3256404VDS8IPC |
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V54C3256(16/80/40)4VD*I
256Mbit SDRAM, INDUSTRIAL TEMPERATURE
3.3 VOLT, TSOP II / FBGA PACKAGE
16M X 16, 32M X 8, 64M X 4
V54C3256(16/80/40)4VD*I Rev. 1.1 May 2006
6
7PC
7
8PC
System Frequency (fCK)
166 MHz
143 MHz
125 MHz
Clock Cycle Time (tCK3)
6 ns
7 ns
8 ns
Clock Access Time (tAC3) CAS Latency = 3
5.4 ns
6 ns
Clock Access Time (tAC2) CAS Latency = 2
5.4 ns
6 ns
Features
■ 4 banks x 4Mbit x 16 organization
■ 4 banks x 8Mbit x 8 organization
■ 4 banks x16Mbit x 4 organization
■ High speed data transfer rates up to 166 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 8192 cycles/64 ms
■ Available in 54 Pin TSOP II, 60 Ball FBGA, 54
Ball FBGA
■ LVTTL Interface
■ Single +3.3 V
±0.3 V Power Supply
■ Industrial Temperature (TA): -40C to +85C
Description
The V54C3256(16/80/40)4VD*I is a four bank
Synchronous DRAM organized as 4 banks x 4Mbit
x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit x 4.
The
V54C3256(16/80/40)4VD*I
achieves
high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T/S
6
7PC
7
8PC
Std.
L
U
-40
°C to +85°C
I
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V54C3256404VS | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| V54C3256404VT | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| V54C3256804VAB | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| V54C3256804VAT | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
| V54C3256804VB | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4 |
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