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參數(shù)資料
| 型號(hào)： | V54C316162VAT10 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 1M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO50 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-50 |
| 文件頁數(shù)： | 1/61頁 |
| 文件大小： | 916K |
| 代理商： | V54C316162VAT10 |
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MOSEL VITELIC
1
V54C316162VA
HIGH PERFORMANCE
3.3 VOLT 1M X 16 SYNCHRONOUS DRAM
2 BANKS X 512Kbit X 16
V54C316162VA Rev. 1.0 January 1998
PRELIMINARY
CAS Latency = 3
8
10
12
System Frequency (fCK)
125 MHz
100 MHz
83 MHz
Clock Cycle Time (tCK3)
8 ns
10 ns
12 ns
Clock Access Time (tAC3)
7 ns
8 ns
9 ns
Features
s 2 banks x 512Kbit x 16 organization
s High speed data transfer rates up to 125 MHz
s Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s Single Pulsed RAS Interface
s Dual Data Mask for Byte Control
s Dual Banks controlled by A11
s Programmable CAS Latency: 1, 2, 3
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
s Multiple Burst Read with Single Write Operation
s Automatic and Controlled Precharge Command
s Random Column Address every CLK (1-N Rule)
s Suspend Mode and Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 50 Pin 400 mil TSOP-II
s LVTTL Interface
s Single +3.3 V
±0.3 V Power Supply
Description
The V54C316162VA is a dual bank Synchronous
DRAM organized as 2 banks x 512Kbit x 16. The
V54C316162VA achieves high speed data transfer
rates up to 125 MHz by employing a chip architec-
ture that prefetches multiple bits and then synchro-
nizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the two memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
125 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
8
10
12
Std.
0
°C to 70 °C
Blank
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V54C316162VC | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162VC-5 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162VC-55 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162VC-6 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
| V54C316162VC-7 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16 |
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