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參數(shù)資料
| 型號： | V53C8256L |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | High Peformance 3.3 Volt 256K x 8 Bit Fast Page Mode CMOS Dynamic RAM(高性能3.3V 256Kx8快速頁面模式動態(tài)RAM) |
| 中文描述： | 高Peformance 3.3伏256K × 8位快速頁面模式的CMOS動態(tài)RAM（高性能3.3 256Kx8快速頁面模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 146K |
| 代理商： | V53C8256L |
15
V53C8256L Rev. 1.3 February 1999
MOSEL V ITELIC
V53C8256L
Fast Page Mode provides sustained data rates
up to 25 MHz for applications that require high data
rates such as bit-mapped graphics or high-speed
signal processing. The following equation can be
used to calculate the maximum data rate:
Data Output Operation
The V53C8256L Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition
enables the transfer of data to and from the
selected row address in the Memory Array. A RAS
high transition disables data transfer and latches
the output data if the output is enabled. After a
memory cycle is initiated with a RAS low transition,
a CAS low transition or CAS low level enables the
internal I/O path. A CAS high transition or a CAS
high level disables the I/O path and the output
driver if it is enabled. A CAS low transition while
RAS is high has no effect on the I/O data path or on
the output drivers. The output drivers, when
otherwise enabled, can be disabled by holding OE
high. The OE signal has no effect on any data
stored in the output latches. A WE low level can
also disable the output drivers when CAS is low.
During a Write cycle, if WE goes low at a time in
relationship to CAS that would normally cause the
outputs to be active, it is necessary to use OE to
disable the output drivers prior to the WE low
transition to allow Data In Setup Time (t
DS
) to be
satisfied.
Power-On
After application of the V
CC
supply, an initial
pause of 200
m
s is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the V
CC
current requirement
of the V53C8256L is dependent on the input levels
of RAS and CAS. If RAS is low during Power-On,
the device will go into an active cycle and I
CC
will
exhibit current transients. It is recommended that
RAS and CAS track with V
CC
or be held at a valid
V
IH
during Power-On to avoid current surges.
Table 1. V53C8256L Data Output
Operation for Various Cycle Types
Data Rate
511
t
RC
t
PC
′
+
----------------------------------------
=
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write Cycle
(Early Write)
High-Z
WE-Controlled Write Cycle
(Late Write)
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write Cycles
Data from Addressed
Memory Cell
Fast Page Mode Read
Data from Addressed
Memory Cell
Fast Page Mode Write Cycle
(Early Write)
High-Z
Fast Page Mode Read-Modify-
Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
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