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參數(shù)資料
| 型號： | V53C8256L |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | High Peformance 3.3 Volt 256K x 8 Bit Fast Page Mode CMOS Dynamic RAM(高性能3.3V 256Kx8快速頁面模式動態(tài)RAM) |
| 中文描述： | 高Peformance 3.3伏256K × 8位快速頁面模式的CMOS動態(tài)RAM（高性能3.3 256Kx8快速頁面模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/18頁 |
| 文件大小： | 146K |
| 代理商： | V53C8256L |
MOSEL V ITELIC
1
V53C8256L
HIGH PERFORMANCE
3.3 VOLT 256K x 8 BIT FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C8256L Rev. 1.3 February 1999
HIGH PERFORMANCE
60
Max. RAS Access Time, (t
RAC
)
60 ns
Max. Column Address Access Time, (t
CAA
)
30 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
40 ns
Min. Read/Write Cycle Time, (t
RC
)
120 ns
Features
I
256K x 8-bit organization
I
Fast Page Mode for a sustained data rate
of 25 MHz
I
RAS access time: 60 ns
I
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
I
Refresh Interval: 512 cycles/8 ms
I
Available in 24 pin 300 mil Plastic DIP,
24/26 pin 300 mil SOJ, and 28-pin TSOP-I
packages
I
Single +3.3 V
±
0.3 V power supply
I
TTL Interface
Description
The V53C8256L is a high speed 262,144 x 8 bit
CMOS dynamic random access memory. The
V53C8256L offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered
to allow increased system performance. Fast Page
Mode operation allows random access of up to 512
(x8) bits within a row with cycle times as short as
40ns. Because of static circuitry, the CAS clock is
not in the critical timing path. The flow-through
column address latches allow address pipelining
while relaxing many critical system timing
requirements for fast usable speed. These features
make the V53C8256L ideally suited for graphics,
digital signal processing and high performance
computing systems.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
P
K
T
60
Std.
0
°
C to 70
°
C
Blank
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