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參數(shù)資料
| 型號： | V53C8128HK45 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 128K X 8 EDO DRAM, 45 ns, PDSO24 |
| 封裝： | 0.300 INCH, SOJ-26/24 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 222K |
| 代理商： | V53C8128HK45 |
8
MOSEL-VITELIC
V53C8128H
V53C8128H Rev. 1.1 November 1997
Notes:
1.
ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2.
ICC is dependent upon the number of address transitions. Specified IDD (max.) is measured with a maximum of two
transitions per address cycle in EDO Page Mode.
3.
Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period not
to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VDD.
4.
tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.)
can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5.
Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6.
Measured with a load equivalent to two TTL inputs and 50 pF.
7.
Access time is determined by the longest of tCAA, tCAC and tCAP.
8.
Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds
tRAD (max.).
9.
Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds
tRCD (max.).
10.
Assumes that tRAD ≥ tRAD (max.).
11.
Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12.
tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13.
tWCS (min.) must be satisfied in an Early Write Cycle.
14.
tDS and tDH are referenced to the latter occurrence of CAS or WE.
15.
tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16.
Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17.
An initial 200
s pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
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