參數(shù)資料
型號(hào)： V53C8128HK45
廠商： MOSEL-VITELIC
元件分類： DRAM
英文描述： 128K X 8 EDO DRAM, 45 ns, PDSO24
封裝： 0.300 INCH, SOJ-26/24
文件頁(yè)數(shù)： 1/20頁(yè)
文件大?。?/td> 222K
代理商： V53C8128HK45
1
MOSEL-VITELIC
V53C8128H
V53C8128H Rev. 1.1 November 1997
HIGH PERFORMANCE
35
40
45
50
Max.
RAS Access Time, (t
RAC)
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (tCAA)
18 ns
20 ns
22 ns
24 ns
Min. Fast Page Mode With EDO Cycle Time, (tPC)
14 ns
15 ns
17 ns
19 ns
Min. Read/Write Cycle Time, (tRC)
70 ns
75 ns
80 ns
90 ns
PRELIMINARY
V53C8128H
ULTRA-HIGH PERFORMANCE,
128K X 8 BIT EDO PAGE MODE
CMOS DYNAMIC RAM
Device Usage Chart
Operating
Package Outline
Access Time (ns)
Power
Temperature
Range
K
35
40
45
50
Std.
Mark
0
°C to 70 °C
Blank
Features
s 128K x 8-bit organization
s
RAS access time: 35, 40, 45, 50 ns
s EDO Page Mode supports sustained I/O data
rates up to 71.5 MHz
s Low power dissipation
V53C8128H-50
— Operating Current – 135 mA max
— TTL Standby Current – 2.0 mA max
s Low CMOS Standby Current
V53C8128H – 1.0 mA max
s Read-Modify-Write,
RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s Refresh Interval
V53C8128H – 512 cycles/8 ms
s Available in 26/24 pin 300 mil SOJ package
Description
The V53C8128H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8128H offers a combination of features: EDO
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with extended data out operation allows random
access of up to 256 columns (x8) bits within a row
with cycle times as short as 14 ns. Because of static
circuitry, the
CAS clock is not in the critical timing
path. The flow-through column address latches
allow address pipelining while relaxing many critical
system timing requirements for fast usable speed.
These features make the V53C8128H ideally suited
for graphics, digital signal processing and high
performance Peripherals.
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