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參數(shù)資料
| 型號： | V53C518165AT60 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | DRAM|EDO|1MX16|CMOS|TSOP|50PIN|PLASTIC |
| 中文描述： | 內(nèi)存| EDO公司| 1MX16 |的CMOS |的TSOP | 50PIN |塑料 |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 193K |
| 代理商： | V53C518165AT60 |
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3
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Block Diagram
No. 2 Clock
Generator
Data In
Buffer
Data Out
Buffer
Column
Address
Buffers (10)
Refresh
Controller
Row
Decoder
Refresh
Counter (10)
Voltage Down
Generator
No. 1 Clock
Generator
Row
Address
Buffers (10)
10
16
I/O1 I/O2
I/O16
16
VCC
VCC (internal)
OE
10
10
10
16
1024
1024
x16
Memory Array
1024 x 1024 x 16
Sense Amplifier
I/O Gating
316516500-03
Column
Decoder
A0
UCAS
WE
LCAS
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
10
Absolute Maximum Ratings*
*
Note:
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Capacitance*
T
A
= 25
°
C, V
CC
= 5 V
±
10%, V
SS
= 0 V, f = 1 MHz
*
Note:
Capacitance is sampled and not 100% tested.
Symbol
Parameter
Commercial
Extended
Units
V
N
Power Supply Voltage
-1 to +7
-1 to +7
V
V
DQ
Input/Output Voltage
-0.5 to min (V
CC
+0.5, 7.0)
-0.5 to min (V
CC
+0.5, 7.0)
V
T
BIAS
Temperature Under Bias
-10 to +125
-65 to +135
°
C
T
STG
Storage Temperature
-55 to +125
-65 to +150
°
C
Symbol
Parameter
Min.
Max.
Unit
C
IN1
Address Input
—
5
pF
C
IN2
RAS, UCAS, LCAS,
WE, OE
—
7
pF
C
OUT
Data Input/Output
—
7
pF
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