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參數(shù)資料
| 型號： | V23816-N1018-C312 |
| 廠商： | SIEMENS AG |
| 英文描述： | 3.3 V, 4-Line LVDS Parallel 2.5 GBd Transponder(3.3V, 4線低壓差分信號并行2.5 GBd異頻雷達收發(fā)器) |
| 中文描述： | 3.3伏，四線并行的LVDS 2.5 GBd轉(zhuǎn)發(fā)器（3.3V，四線低壓差分信號并行2.5 GBd異頻雷達收發(fā)器） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 2303K |
| 代理商： | V23816-N1018-C312 |
Fiber Optics
V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km
4
Block Diagram
Functional Signal Description
Transmit Functions
Signal Name
Transceiver IC
REFCLKP/N
D155.52 MHz
REFCLKP/N
Clock
Synthesizer
Clocks
LVTTL
LOCKDET
TXLOCK
High=Locked
Timing
Generator
High= Phase Error
4:1
Parallel
to Serial
Converter
PINP/N[3:0]
622.Bit3= MSB
Diff LVDS
TXDATAP/N[3:0]
PICLKP/N
Diff LVDS
622.08 MHz
TXCLKP/N
TXDP/N
Latch
TSDP/N
RSCLKP/N
TSCLKP/N
Low= Enabled
LVTTL
Timing
POCLKP/N
RXCLKP/N
Diff LVDS
S1:4
POUTP/N[3:0]
RXDABit3= MSB
Diff LVDS
Latch
R
DLEB
LVTTL
Low= Loopback Enabled
RSDP/N
RSCLKP/N
Latch
SDLVPECL
Logic "1"
SDLVTTL
Logic
LVTTL
TXCLKP/N (Internal)
CML
CML
LASER_DISABLE
HLVTTL
Laser
Driver
LVTTL
TX_FAULT
High= TX Fault (Auto Shutoff)
FP Laser
Diode
Monitor
Diode
LVTTL
TX_BIASMON
High=Outside Limits
21310 nm
LC/PC
Clock & Data
Recovery
Data
Clock
OCrystal
Limiting
Post Amp
Data
Data
LOS
LVTTL
RX_LOS
High= RX Loss of Signal
Lock
LVTTL
RX_LOSYNC
High= RX Loss of Synch
PIN
Diode &
Preamp
Data
241310 nm
LC/PC
Single Mode
Fiber
LLEB
CML
LVPECL
1
0
1
0
0
1
1
0
155.52 MHz
Post Amp/CDR
RLPTIME
LVTTL
0
1
SLPTIME
LVTTL
PCLKP/N
Diff LVDS
PCLKP/N
VLOS
1
0
POCLK DIV 4
RSCLKP/N
PHINITP/N
PHERRP/N
PHASE_ERRP/N
Diff LVDS
Diff LVDS
PHASE_INITP/N
Data
LLEB_L
DLEB_L
RESET_L
LVTTL
RESET_L
+3.3V
1
2
3
Level
I/O Pin # Description
TXDATAP0
TXDATAN0
TXDATAP1
TXDATAN1
TXDATAP2
TXDATAN2
TXDATAP3
TXDATAN3
LVDS
I
1
3
7
9
13
15
19
21
Transmit Parallel input data
at 622.08 Mb/s, aligned to
the TXCLKP/N parallel input
clock. TXDATAP/N[3] is the
most significant bit (MSB),
and is the first bit transmit-
ted in the outgoing OC-48
serial data stream. TX-
DATAP/N[3:0] is sampled
on the rising edge of TX-
CLKP. DC coupled and in-
ternally terminated.
Transmit Parallel input
clock, 622.08 MHz, to
which TXDATAP/N[3:0] is
aligned. TXCLK transfers
the data on the TXDATAP/
N inputs into a 4-bit wide
latch in the Transceiver IC.
Data is sampled on the ris-
ing edge of TXCLKP. DC
coupled and internally ter-
minated.
TXCLKP
TXCLKN
LVDS
I
27
25
REFCLKP
REFCLKN
LVPECL
I
31
33
155.52 MHz Transmit Ref-
erence Clock input to the
bit clock frequency synthe-
sizer of the Transceiver IC.
DC coupled and internally
biased.
PHASE_INITP
PHASE_INITN
LVDS
I
37
39
Phase Initialization. Rising
edge of PHASE_INITP will
realign internal timing. DC
coupled. No internal termi-
nation.
Laser Disable. Control in-
put to disable Transmit la-
ser. High = Disable laser.
Pulled low through 1 k
=
resistor.
LASER_
DISABLE
LVTTL
I
49
TXLOCK
LVTTL
O
51
Loss Of Lock alarm for TX
PLL of the Transceiver IC.
High = Locked. Asynchro-
nous output.
PHASE_ERRP
PHASE_ERRN
LVDS
O
45
43
Phase Error. Active high.
PHASE_ERRP will pulses
high during each clock cy-
cle for which there is a po-
tential set-up and hold
timing violation between
the internal byte clock of
the Transceiver IC and the
TXCLK timing domains.
DC coupled and internally
terminated.
Signal Name
Level
I/O Pin # Description
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相關代理商/技術參數(shù) |
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| V23816-N1018-L312 | 制造商:Infineon Technologies AG 功能描述:4 Line LVDS Parallel 2.5 GBd Transponder 60-Pin |
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| V23818-C18-L36 | 功能描述:TXRX SGL MODE ATM 155MBD 1300NM RoHS:否 類別:光電元件 >> 光纖 - 收發(fā)器 系列:- 標準包裝:20 系列:* |
| V23818-C18-L37 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Small Form Factor Single Mode 1300 nm Multirate up to 155 Mbit/s Transceiver 2x5 Pinning with LC⑩ Connector |
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