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參數(shù)資料
| 型號： | V23816-N1018-C312 |
| 廠商： | SIEMENS AG |
| 英文描述： | 3.3 V, 4-Line LVDS Parallel 2.5 GBd Transponder(3.3V, 4線低壓差分信號并行2.5 GBd異頻雷達(dá)收發(fā)器) |
| 中文描述： | 3.3伏，四線并行的LVDS 2.5 GBd轉(zhuǎn)發(fā)器（3.3V，四線低壓差分信號并行2.5 GBd異頻雷達(dá)收發(fā)器） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 2303K |
| 代理商： | V23816-N1018-C312 |
Fiber Optics
V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km
3
tional to the intensity of the incoming light. The trans-imped-
ance amplifier performs current-to-voltage conversion, and the
non-limiting post-amplifier quantizes the signal into a digital out-
put.
The receiver contains a RX power monitor output, which is a
voltage output directly proportional to the average optical input
power.
The Limiting Post-Amplifier provides additional voltage amplifi-
cation, and also provides a Loss Of Signal (RX_LOS) indicator.
LOS will occur at a RX input power level less than the specified
RX Sensitivity, and is an indication that the RX is taking bit
errors.
The Clock and Data Recovery (CDR) uses a PLL based approach
to recover the high speed clock from the incoming serial data
stream. A lock alarm, RX_LOSYNC, indicates if the CDR has lost
synchronization. This will occur if the input RX power level is
very low (below the LOS threshold level), or if the input data
rate is outside the specified frequency tolerance. In these
cases, the CDR will phase lock to a Crystal Oscillator so it can
produce a valid clock output, with a frequency accuracy of
±
20
ppm. In both cases of Loss Of Signal or Loss Of Synchroniza-
tion, the Transceiver IC will force all the RX output data bits,
RXDATAP/N [3:0] to a constant zero state.
Receiver (Demux section)
The incoming serial data is latched into the Transceiver IC by
the recovered clock. The data and clock are applied to a 4 bit
wide Serial-to-Parallel Converter (Demux), which demultiplexes
the data into a parallel format. The first bit received, i.e. the
MSB which is transmitted first in the serial data stream, is
placed into the highest order bit of the parallel output word, i.e.
Bit 3 = MSB. The Transceiver IC, however, does not perform a
frame alignment function. This means that the parallel output
word will contain the bits in the correct order, however, the
position of the bits within the parallel output word may be
shifted by an arbitrary amount between 0 and 4 bits. It is the
function of downstream framer logic to realign the bits.
The retimed RX output data, RXDATAP/N[3:0], is output at a
622.08 Mb/s data rate. The output clock, RXCLKP/N, is at
622.08 MHz. The RXDATAP/N[3:0] data is updated on the falling
edge of RXCLKP (See RX Output Timing Diagram).
Loopback Operation
Four loopback modes of operation are provided.
Line Loopback
is enabled with the LLEB_L input. In Line Loop-
back operation, the RX Serial Data and Clock inputs to the
Transceiver IC (RSDP/N and RSCLKP/N) are routed directly to
the TX Serial outputs of the IC (TSDP/N and TSCLKP/N). This
effectively eliminates the Transceiver IC from the signal path.
Diagnostic Loopback
is enabled with the DLEB_L input. In Diag-
nostic Loopback operation, the TX output Serial Data and Clock
of the Transceiver IC (TSDP/N and TSCLKP/N) are routed
directly to the RX Serial Data and Clock inputs of the IC (RSDP/
N and RSCLKP/N). This effectively eliminates the optical and
electro-optical components from the signal path.
Reference Loop Time
is enabled with the RLPTIME input. In
Reference Loop Time operation, a divide-by-4 version of the
POCLKP/N output of the RX is used as the reference clock
input to the TX.
Serial Loop Time
is enabled with the SLPTIME input. In Serial
Loop Time operation, the recovered high-speed clock (RSCLKP/
N) from the RX section is used in place of the synthesized
transmit clock.
J itter
The transponder is specified to meet the Sonet J itter perfor-
mance as outlined in ITU-T G.958 and Bellcore GR-253.
J itter Generation
is defined as the amount of jitter that is gener-
ated by the transponder. The J itter Generation specifications
are referenced to the optical OC-48 signals. If no or minimum
jitter is applied to the electrical inputs of the transmitter, then
J itter Generation can simply be defined as the amount of jitter
on the TX Optical output. The Sonet specifications for J itter
Generation are 0.01 UI rms, maximum and 0.1 UI p-p, maxi-
mum. Both are measured with a 12 KHz-20 MHz filter in line. A
UI is a Unit Interval, which is equivalent to one bit slot. At OC-
48, the bit slot is 400 ps, so the J itter Generation specification
translates to 4 ps rms, max. and 40 ps p-p, max.
J itter Tolerance
is defined as the amount of jitter applied to the
RX Optical input that the receiver will tolerate while producing
less than a 1 dB penalty in RX Sensitivity. The minimum J itter
Tolerance levels are normally expressed as a mask of jitter
amplitude versus jitter frequency. Measured J itter Tolerance
levels must be greater than the mask limits. The J itter Toler-
ance mask specified in the Bellcore GR-253 document covers
jitter frequencies down to 10 Hz. The transponder will be
designed to meet this mask.
Sonet J itter Transfer Mask (ITU-T G.958 & Bellcore GR-253)
Sonet J itter Tolerance Mask (Bellcore GR-253)
J itter Transfer
is defined as the ratio of output jitter to input jit-
ter. Referenced to an optical transponder, it is defined as the
ratio of TX Optical Output J itter to RX Optical Input J itter. To
measure J itter Transfer, the transponder must be operating in
electrical loopback mode, with the RX electrical outputs looped
back into the TX electrical inputs. J itter Transfer is defined to be
less than 0.1 dB up to 2 MHz, then dropping at –20 dB decade
thereafter, per ITU-T G.958 and Bellcore GR-253. The J itter
Transfer must be less than the following mask limits.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V23816-N1018-L312 | 制造商:Infineon Technologies AG 功能描述:4 Line LVDS Parallel 2.5 GBd Transponder 60-Pin |
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| V23818-C18-L36 | 功能描述:TXRX SGL MODE ATM 155MBD 1300NM RoHS:否 類別:光電元件 >> 光纖 - 收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:20 系列:* |
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