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參數(shù)資料
| 型號： | V23816-N1018-C312 |
| 廠商： | SIEMENS AG |
| 英文描述： | 3.3 V, 4-Line LVDS Parallel 2.5 GBd Transponder(3.3V, 4線低壓差分信號并行2.5 GBd異頻雷達(dá)收發(fā)器) |
| 中文描述： | 3.3伏，四線并行的LVDS 2.5 GBd轉(zhuǎn)發(fā)器（3.3V，四線低壓差分信號并行2.5 GBd異頻雷達(dá)收發(fā)器） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 2303K |
| 代理商： | V23816-N1018-C312 |
Fiber Optics
V23816-N1018-C/L312, 3.3V, 4-Line LVDS Parallel 2.5GBd Transp.OC-48 SONET/SDH SR, 2km
2
DESCRIPTION
The Infineon single mode SONET/SDH transponder is compli-
ant with the Bellcore GR-253, ITU-T G.957 and ITU-T G.958
specifications. It is also compliant with the OIF99.102 proposal.
The transmitter section consists of a multiplexer (Mux), laser
driver, Fabry Perot (FP) laser diode and pigtail single mode fiber
with LC/PC or SC/PC 0 ° termination. The receiver section
consists of a multimode fiber pigtail with LC/PC or SC/PC termi-
nation, a packaged PIN photodiode and preamplifier, postampli-
fier, clock and data recovery (CDR), and a demultiplexer
(Demux). The Mux and Demux functions are integrated
together onto a single Transceiver IC. The 622.08 MHz parallel
data interface frees the user from the concerns of pcb layout at
2.5 Gb/s. The pluggable connector blind mates easily to the
customer pcb, and allows the transponder to be removed prior
to any solder reflow or washing of the users pcb.
The transponder operates from a single +3.3 V power supply.
The electrical interface is via a 60 pin pluggable connector. The
transmit and receive electrical signals each consist of 4 parallel
differential LVDS data, and a differential LVDS clock. The trans-
mit input data and clock lines, and the receive output data and
clock lines, are all internally biased and terminated. All lines are
DC coupled to the interface connector.
The transponder is designed to transmit and receive serial OC-
48 (2488.32 Mb/s) data over standard non-dispersion-shifted
single mode fiber at a wavelength of 1310 nm.
Transmitter (Mux Section)
Please refer to the transponder block diagram.
The transmitter accepts a 4 bit wide parallel input data word,
TXDATAP/N[3:0], at a 622.08 Mb/s data rate. The TX input clock,
TXCLKP/N, is synchronous with the incoming data, at a fre-
quency of 622.08 MHz. This clock is used to load the data into a
4-bit latch. The data is read in on the rising edge of the positive
input clock. (See TX Input Timing Diagram).
A reference input clock, REFCLKP/N, at 155.52 MHz, is sup-
plied as a reference input to the high speed Clock Synthesizer.
The high speed output of the clock synthesizer will clock the
Timing Generator and the Parallel-to-Serial Converter. The Paral-
lel-to-Serial Converter will output the retimed data as a serial bit
stream, TSDP/N, at 2488.32 Mb/s data rate. Bit 3 of the
TXDATAP/N parallel input word is the MSB, and is transmitted
first in the data stream. Bit 0, the LSB, is transmitted last.
The output of the high speed Clock Synthesizer, which is inter-
nally set to 2488.32 MHz, is tapped off the Timing Generator,
and is divided to 622.08 MHz. This output (PCLKP/N) is
intended to be used as a reference clock for TX upstream logic.
The PHASE_INITP/N input signal is used to realign the internal
timing of the Timing Generator by resetting and centering the
FIFO in the Transceiver IC. The realignment will occur on the ris-
ing edge of PHASE_INITP which must be held high for at least
10 ns.
The PHASE_ERRP/N output will pulse high during each clock
cycle when there is a potential set-up & hold timing violation
between the internal byte clock and the TXCLKP/N input, indi-
cating that PHASE_INITP/N must be strobed.
If the Reference Clock input, REFCLKP/N, is derived from and is
synchronous with the TX Byte Clock, TXCLKP/N, then there
should never be any short setup and hold times between the
two timing domains, and the FIFO should never need to be
recentered. However, if the REFCLKP/N input is, for instance,
produced by a free running oscillator, then such potential viola-
tions may exist. When FIFO realignment occurs, up to 10 bytes
of data will be lost. Automatic FIFO realignment can be enabled
by simply connecting the PHASE_ERRP/N output directly to the
PHASEINITP/N input. The user can also take the PHASE_ERRP/
N output, process it and send a signal to the PHASE_INITP/N in
such a way that idle bytes are lost during the realignment pro-
cess.
The TX Clock Synthesizer section provides a lock alarm output
signal, TXLOCK, which indicates if the clock synthesizer is prop-
erly phase locked.
Transmitter (Electro-Optical Section)
The serial data output, TSDP/N, of the Transceiver IC is input to
a laser driver IC. The laser driver provides both bias and modula-
tion to a laser diode. The laser bias current is controlled by a
closed-loop circuit, which regulates the output average power
of the laser over conditions of temperature and aging. The Mon-
itor PIN diode, which is mechanically built into the laser, pro-
vides a feedback signal to the laser driver, and prevents the
laser power from exceeding the factory preset operating limits.
The laser driver includes an eye safety feature that will automat-
ically shut off power to the laser if a fault condition occurs
which causes excessively high laser bias current or excessively
high average output power. Such a fault will be indicated on the
TX_FAULT output. The fault can be cleared by cycling DC
power, or by strobing the RESET_L input.
The Mux and Laser Driver can be reset with the RESET_L input.
During the time that RESET_L is held active, there will be no
optical output from the transmitter. The RESET_L input will
clear any fault indication that has occurred on the TX_FAULT
output.
The laser can be switched off at any time with the
LASER_DISABLE input.
The TX_BIASMON output is provided as an alarm to indicate if
the laser bias current is outside of the normal operating range.
This output can be used to monitor the aging of the laser.
The laser diode is a Fabry-Perot type, which, due to the cavity
nature of its design, will emit light at several longitudinal wave-
lengths, or modes centered about 1310 nm. This type of laser is
suitable for the short reach transmission over single-mode fiber
that this transponder is intended for. The laser has a single-
mode fiber pigtail, which is terminated in an LC/PC 0 ° optical
connector.
Receiver (Electro-Optical Section)
The input light to the RX is coupled from the transmission fiber
into a PIN/Preamp assembly on the transponder. The PIN/
Preamp contains a multi-mode fiber pigtail, which is terminated
in an LC/PC or SC/PC 0 ° optical connector. The multi-mode
fiber pigtail has a larger core diameter (50 μm) than the single-
mode transmission fiber (9 μm). Therefore, all the light from the
single-mode fiber is coupled into the larger diameter core of the
multi-mode pigtail.
The PIN/Preamp contains a PIN photodiode, trans-impedance
amplifier and non-limiting post-amplifier in one package. The
PIN diode produces a current output, which is directly propor-
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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