參數(shù)資料
型號(hào): UT62L1024LC-55LL
廠商: Electronic Theatre Controls, Inc.
英文描述: 128K X 8 BIT LOW POWER CMOS SRAM
中文描述: 128K的× 8位低功耗CMOS SRAM
文件頁(yè)數(shù): 6/14頁(yè)
文件大小: 235K
代理商: UT62L1024LC-55LL
UTRON
UT62L1024
Rev. 1.7
128K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5)
t
WC
UTRON TECHNOLOGY INC. P80033
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
t
AW
t
CW1
t
AS
t
WP
t
WHZ
t
OW
t
DW
t
DH
t
CW2
t
WR
Address
CE1
CE2
WE
Dout
Din
Data Valid
High-Z
(4)
(4)
WRITE CYCLE 2
(
1
CE
and CE2 Controlled)
(1,2,5)
t
WC
t
AW
t
CW1
t
AS
t
WR
t
CW2
t
WP
t
WHZ
t
DW
t
DH
Data Valid
Address
CE1
CE2
WE
Dout
Din
High-Z
Notes :
1.
WE
or
1
CE
must be HIGH or CE2 must be LOW during all address transitions.
2. A write occurs during the overlap of a low
1
CE
, a high CE2 and a low
WE
.
3. During a
WE
controlled with write cycle with
OE
LOW, t
WP
must be greater than t
WHZ
+t
DW
to allow the I/O drivers to turn
off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
4. If the
1
CE
LOW transition occurs simultaneously with or after
WE
LOW transition, the outputs remain in a high Impedance
state.
6. t
OW
and t
WHZ
are specified with C
L
=5pF. Transition is measured
±
500mV from steady state.
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