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參數(shù)資料
| 型號(hào)： | UT62L1024LC-55LL |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 128K X 8 BIT LOW POWER CMOS SRAM |
| 中文描述： | 128K的× 8位低功耗CMOS SRAM |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 235K |
| 代理商： | UT62L1024LC-55LL |
UTRON
UT62L1024
Rev. 1.7
128K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(Ta=25
℃
, f=1.0MHz)
PARAMETER
SYMBOL MIN.
Input Capacitance
C
IN
Input/Output Capacitance
C
I/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V~3.6V , Ta = 0
℃
to +70
℃
)
(1) READ CYCLE
PARAMETER
SYMBOL
UT62L1024-35 UT62L1024-55 UT62L1024-70
UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
t
RC
35
Address Access Time
t
AA
Chip Enable Access Time
t
ACE1
, t
ACE2
Output Enable Access Time
t
OE
Chip Enable to Output in Low-Z
t
CLZ1
*, t
CLZ2
*
10
Output Enable to Output in Low-Z t
OLZ
*
5
Chip Disable to Output in High-Z
t
CHZ1
*, t
CHZ2
*
Output Disable to Output in High-Z t
OHZ
*
Output Hold from Address Change t
OH
5
(2) WRITE CYCLE
PARAMETER
SYMBOL
UT62L1024-35 UT62L1024-55 UT62L1024-70
UNIT
MIN.
Write Cycle Time
t
WC
35
Address Valid to End of Write
t
AW
30
Chip Enable to End of Write
t
CW1
, t
CW2
30
Address Set-up Time
t
AS
0
Write Pulse Width
t
WP
25
Write Recovery Time
t
WR
0
Data to Write Time Overlap
t
DW
20
Data Hold from End of Write-Time t
DH
0
Output Active from End of Write
t
OW
*
5
Write to Output in High-Z
t
WHZ
*
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC. P80033
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
MAX.
6
8
UNIT
pF
pF
-
-
0.4V to 2.4V
5ns
1.5V
C
L
=50pF, I
OH
/I
OL
=-1mA/2mA
-
55
-
-
-
10
5
-
-
5
-
70
-
-
-
10
5
-
-
5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
35
35
25
-
-
25
25
-
55
55
30
-
-
30
30
-
70
70
35
-
-
35
35
-
-
-
MAX. MIN. MAX. MIN. MAX.
-
55
-
-
50
-
-
50
-
-
0
-
-
40
-
-
0
-
-
25
-
-
0
-
-
5
-
15
-
20
70
60
60
0
45
0
30
0
5
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
25
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UT62L1024LC-70L | 128K X 8 BIT LOW POWER CMOS SRAM |
| UT62L1024LC-70LL | 128K X 8 BIT LOW POWER CMOS SRAM |
| UT62L1024LS-35L | 128K X 8 BIT LOW POWER CMOS SRAM |
| UT62L1024LS-35LL | 128K X 8 BIT LOW POWER CMOS SRAM |
| UT62L1024LS-55L | 128K X 8 BIT LOW POWER CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UT62L1024LC-70L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT62L1024LC-70LL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT62L1024LS-35L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT62L1024LS-35LL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
| UT62L1024LS-55L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K X 8 BIT LOW POWER CMOS SRAM |
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