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| 型號： | uPSD3412C-24U6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM |
| 中文描述： | 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和16Kbit SRAM的 |
| 文件頁數(shù)： | 38/152頁 |
| 文件大小： | 796K |
| 代理商： | UPSD3412C-24U6T |
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UPSD3212C, UPSD3212CV
38/152
INTERRUPT SYSTEM
There are interrupt requests from 10 sources as
follows (see Figure 16, page 39).
I
INT0 External Interrupt
I
2nd USART Interrupt
I
Timer 0 Interrupt
I
I
2
C Interrupt
I
INT1 External Interrupt (or ADC Interrupt)
I
Timer 1 Interrupt
I
USART Interrupt
I
Timer 2 Interrupt
External Int0
– The INT0 can be either level-active or transition-
active depending on Bit IT0 in register TCON.
The flag that actually generates this interrupt is
Bit IE0 in TCON.
– When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
– If the interrupt was level activated then the inter-
rupt request flag remains set until the requested
interrupt is actually generated. Then it has to de-
activate the request before the interrupt service
routine is completed, or else another interrupt
will be generated.
Timer 0 and 1 Interrupts
– Timer 0 and Timer 1 Interrupts are generated by
TF0 and TF1 which are set by an overflow of
their respective Timer/Counter registers (except
for Timer 0 in Mode 3).
– These flags are cleared by the internal hard-
ware when the interrupt is serviced.
Timer 2 Interrupt
– Timer 2 Interrupt is generated by TF2 which is
set by an overflow of Timer 2. This flag has to be
cleared by the software - not by hardware.
– It is also generated by the T2EX signal (Timer 2
External Interrupt P1.1) which is controlled by
EXEN2 and EXF2 Bits in the T2CON register.
I
2
C Interrupt
– The interrupt of the I
2
C is generated by Bit INTR
in the register S2STA.
– This flag is cleared by hardware.
External Int1
– The INT1 can be either level active or transition
active depending on Bit IT1 in register TCON.
The flag that actually generates this interrupt is
Bit IE1 in TCON.
– When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
– If the interrupt was level activated then the inter-
rupt request flag remains set until the requested
interrupt is actually generated. Then it has to de-
activate the request before the interrupt service
routine is completed, or else another interrupt
will be generated.
– The ADC can take over the External INT1 to
generate an interrupt on conversion being com-
pleted
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| UPSD3422E-40T6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3422E-40U6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| UPSD3422EB40T6 | 功能描述:8位微控制器 -MCU Turbo 8032 MCU w/USB & Programmable Logic RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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